Abstract: A system applies bottleneck analysis for design and optimization of computing systems. In particular, the system constructs a bottleneck model, including a bottleneck cost graph for a workload or a function, through which factors corresponding to the execution costs of an arbitrary processor can be modeled. By using the bottleneck analysis, the system can determine bottleneck factors for an obtained cost value (e.g., time taken by an application's execution on a processor) and can reason about obtained high cost. The system determines and uses information about parameters impacting bottlenecks for execution costs and their approximate relationship with the bottlenecks to produce an optimized hardware-software configuration for execution of one or more workloads. Systematic, bottleneck-guided analysis and optimization can introduce explainability in the design and optimization process and can achieve more efficient design configurations much faster.

Abstract: Various embodiments of a system and associated method for generating a valid mapping for a computational loop on a CGRA are disclosed herein. In particular, the method includes generating randomized schedules within particular constraints to explore greater mapping spaces than previous approaches. Further, the system and related method employs a feasibility test to test validity of each schedule such that mappings are only generated from valid schedules.

Abstract: A method for detecting and recovery from a soft error in a computing device is provided. In examples discussed herein, the method can be performed to detect soft errors that may occur during execution of a predefined critical instruction(s) and/or has been propagated in the computing device prior to the execution of the predefined critical instruction(s). Specifically, a software compiler may be used to embed an error detector block(s) after the predefined critical instruction(s). In this regard, the error detector block(s) can be executed after the predefined critical instruction(s) to detect the soft error. Accordingly, it may be possible to invoke a diagnosis routine to determine severity of the detected soft error and take appropriate action against the detected soft error. As such, it may be possible to protect the execution of the predefined critical instruction(s) concurrent to eliminating vulnerable voting intervals and reducing soft error detection overhead.

Abstract: Various embodiments for systems and methods for cooperative driving of connected autonomous vehicles using responsibility-sensitive safety (RSS) rules are disclosed herein. The CAV system integrates proposed RSS rules with CAV's motion planning algorithm to enable cooperative driving of CAVs. The CAV system further integrates a deadlock detection and resolution system for resolving traffic deadlocks between CAVs. The CAV system reduces redundant calculation of dependency graphs.

Abstract: A method for detecting and recovery from a soft error in a computing device is provided. In examples discussed herein, the method can be performed to detect soft errors that may occur during execution of a predefined critical instruction(s) and/or has been propagated in the computing device prior to the execution of the predefined critical instruction(s). Specifically, a software compiler may be used to embed an error detector block(s) after the predefined critical instruction(s). In this regard, the error detector block(s) can be executed after the predefined critical instruction(s) to detect the soft error. Accordingly, it may be possible to invoke a diagnosis routine to determine severity of the detected soft error and take appropriate action against the detected soft error. As such, it may be possible to protect the execution of the predefined critical instruction(s) concurrent to eliminating vulnerable voting intervals and reducing soft error detection overhead.

Abstract: Various embodiments of a system and associated method for generating a valid mapping for a computational loop on a CGRA are disclosed herein. In particular, the method includes generating randomized schedules within particular constraints to explore greater mapping spaces than previous approaches. Further, the system and related method employs a feasibility test to test validity of each schedule such that mappings are only generated from valid schedules.

Abstract: Various embodiments of an intersection management system for managing autonomous vehicles approaching an intersection in which a Time of Arrival, Velocity of Arrival, and path trajectory are calculated for each approaching vehicle are disclosed.

Abstract: Systems and methods for implementing a lightweight checkpoint technique for resilience against soft errors are disclosed. The technique provides effective, safe, and timely soft error detection and recovery using software. In an exemplary aspect, resilience against data flow errors and control flow errors is provided in critical or mixed-critical applications in each basic block or at critical basic blocks. Verified register preservation is provided at each basic block, along with memory preservation checkpoints. In this manner, soft errors are quickly detected and addressed. The register and memory preservation further allows for safe re-execution from recoverable soft errors. Control flow errors can also be detected at the beginning and/or end of each basic block.

Abstract: Various embodiments of an intersection management system for managing autonomous vehicles approaching an intersection in which a Time of Arrival, Velocity of Arrival, and path trajectory are calculated for each approaching vehicle are disclosed.

Abstract: A coarse-grained reconfigurable array includes a processing element array, instruction memory circuitry, data memory circuitry, and an instruction fetch unit. The processing element array includes a number of processing elements. The instruction memory circuitry is coupled to the processing element array and configured to store a set of instructions. During each one of a number of processing cycles, the instruction memory circuitry provides instructions from the set of instructions to the processing elements. The instruction fetch unit is coupled to the processing element array and the instruction memory circuitry and configured to receive a result of a conditional instruction evaluated by one of the processing elements and provide the instruction fetch signals based at least in part on the result of the conditional instruction such that only instructions associated with a correct branch of the conditional instruction are provided to the plurality of processing elements.

Abstract: A method for detecting and recovery from a soft error in a computing device is provided. In examples discussed herein, the method can be performed to detect soft errors that may occur during execution of a predefined critical instruction(s) and/or has been propagated in the computing device prior to the execution of the predefined critical instruction(s). Specifically, a software compiler may be used to embed an error detector block(s) after the predefined critical instruction(s). In this regard, the error detector block(s) can be executed after the predefined critical instruction(s) to detect the soft error. Accordingly, it may be possible to invoke a diagnosis routine to determine severity of the detected soft error and take appropriate action against the detected soft error. As such, it may be possible to protect the execution of the predefined critical instruction(s) concurrent to eliminating vulnerable voting intervals and reducing soft error detection overhead.

Abstract: In embodiments, an apparatus for intersection management of autonomous or semi-autonomous vehicles may include an input interface to receive an intersection crossing request from one or more autonomous or semi-autonomous vehicles, the request including vehicle data; an output interface coupled to a transmitter, and an analyzer coupled to the input interface and to the output interface to process the request, based, at least in part, on the vehicle data, to generate a command including a crossing velocity and a time to assume the crossing velocity, and cause the transmitter, via the output interface, to transmit the command to the requesting vehicle. Other and related embodiments are also described.

Abstract: Systems and methods for implementing a lightweight checkpoint technique for resilience against soft errors are disclosed. The technique provides effective, safe, and timely soft error detection and recovery using software. In an exemplary aspect, resilience against data flow errors and control flow errors is provided in critical or mixed-critical applications in each basic block or at critical basic blocks. Verified register preservation is provided at each basic block, along with memory preservation checkpoints. In this manner, soft errors are quickly detected and addressed. The register and memory preservation further allows for safe re-execution from recoverable soft errors. Control flow errors can also be detected at the beginning and/or end of each basic block.

Abstract: Methods, apparatuses, systems, and implementations of a zero silent data corruption (ZDC) compiler technique are disclosed. The ZDC technique may use an effective instruction duplication approach to protect programs from soft errors. The ZDC may also provide an effective control flow checking mechanism to detect most control flow errors. The ZDC technique may provide a failure percentage close to zero while incurring a lower performance overhead than prior art systems. The ZDC may also be effectively applied in a multi-thread environment.

Abstract: In embodiments, an apparatus for intersection management of autonomous or semi-autonomous vehicles may include an input interface to receive an intersection crossing request from one or more autonomous or semi-autonomous vehicles, the request including vehicle data; an output interface coupled to a transmitter, and an analyzer coupled to the input interface and to the output interface to process the request, based, at least in part, on the vehicle data, to generate a command including a crossing velocity and a time to assume the crossing velocity, and cause the transmitter, via the output interface, to transmit the command to the requesting vehicle. Other and related embodiments are also described.

Abstract: Methods, apparatuses, systems, and implementations of a zero silent data corruption (ZDC) compiler technique are disclosed. The ZDC technique may use an effective instruction duplication approach to protect programs from soft errors. The ZDC may also provide an effective control flow checking mechanism to detect most control flow errors. The ZDC technique may provide a failure percentage close to zero while incurring a lower performance overhead than prior art systems. The ZDC may also be effectively applied in a multi-thread environment.

Abstract: A compiler tool-chain may automatically compile an application to execute on a limited local memory (LLM) multi-core processor by including automated heap management transparently to the application. Management of the heap in the LLM for the application may include identifying access attempts to a program variable, transferring the program variable to the LLM, when not already present in the LLM, and returning a local address for the program variable to the application. The application then accesses the program variable using the local address transparently without knowledge about data in the LLM. Thus, the application may execute on a LLM multi-core processor as if the LLM multi-core processor has an unlimited heap space.

Abstract: The present invention discloses a solution to accelerate control flow loops by utilizing the branch outcome. The embodiments of the invention eliminate fetching and execution of unnecessary operations and also the overhead due to predicate communication thus overcoming the inefficiencies associated with existing techniques. Experiments on several benchmarks are also disclosed, demonstrating that the present invention achieves optimal acceleration with minimum hardware overhead.

Abstract: Software Managed Manycore (SMM) architectures with scratch pad memory for reach core are a promising solution for scaling memory. In these architectures the code and data of the tasks mapped to the cores is explicitly managed by the compiler and often require inter-procedural information and analysis. But, a call graph of the program does not have enough information, and the Global CFG has too much information. Most new techniques informally define and use GCCFG (Global Call Control Flow Graph)—a whole program representation that succinctly captures the control-flow and function call information—to perform inter-procedural analysis. Constructing GCCFGs for several cases in common applications. The present disclosure provides unique graph transformations to formally and correctly construct GCCFGs for optimal compiler management of manycore systems.

Abstract: Methods and apparatus for managing stack data in multi-core processors having scratchpad memory or limited local memory. In one embodiment, stack data management calls are inserted into software in accordance with an integer linear programming formulation and a smart stack data management heuristic. In another embodiment, stack management and pointer management functions are inserted before and after function calls and pointer references, respectively. The calls may be inserted in an automated fashion by a compiler utilizing an optimized stack data management runtime library.