Abstract: Methods, apparatus, systems, and articles of manufacture are described to perform current mode sampling with a feed forward equalizer. An example apparatus includes a transistor operable to convert an input voltage signal from a linear equalizer into a current; a first switch to enable and disable based on a first clock signal; a second switch to enable and disable based on a second clock signal; and a capacitor to: charge based on the current when the first switch is enabled; and discharge when the second switch is enabled.

Abstract: Methods, apparatus, systems, and articles of manufacture are described to perform current mode sampling with a feed forward equalizer. An example apparatus includes a transistor operable to convert an input voltage signal from a linear equalizer into a current; a first switch to enable and disable based on a first clock signal; a second switch to enable and disable based on a second clock signal; and a capacitor to: charge based on the current when the first switch is enabled; and discharge when the second switch is enabled.

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.