Abstract: In one embodiment, quasi-Output Queue behavior of a packet switching device is achieved using virtual output queue (VOQ) ordering independently determined for each particular output queue (OQ), including using maintained latency information of the VOQs of the particular OQ. In one embodiment, all packets from all VOQs with a same port-priority destination experience similar latency within specific time-window, which is similar to the packet service provided by an Output Queue switch architecture. In one embodiment, all input ports that send traffic to same output port-priority receive bandwidth which is proportional to their bandwidth demand divided by total bandwidth. Prior approaches that emulate the performance of an OQ switch architecture require complex and time-consuming scheduling determinations and do not scale. Independently determining the order for sending packets from the VOQs associated with each particular OQ provides a scalable and implementable system with quasi-Output Queue behavior.

Abstract: In one embodiment, quasi-Output Queue behavior of a packet switching device is achieved using virtual output queue (VOQ) ordering independently determined for each particular output queue (OQ), including using maintained latency information of the VOQs of the particular OQ. In one embodiment, all packets from all VOQs with a same port-priority destination experience similar latency within specific time-window, which is similar to the packet service provided by an Output Queue switch architecture. In one embodiment, all input ports that send traffic to same output port-priority receive bandwidth which is proportional to their bandwidth demand divided by total bandwidth. Prior approaches that emulate the performance of an OQ switch architecture require complex and time-consuming scheduling determinations and do not scale. Independently determining the order for sending packets from the VOQs associated with each particular OQ provides a scalable and implementable system with quasi-Output Queue behavior.

Abstract: In one embodiment, quasi-Output Queue behavior of a packet switching device is achieved using virtual output queue (VOQ) ordering independently determined for each particular output queue (OQ), including using maintained latency information of the VOQs of the particular OQ. In one embodiment, all packets from all VOQs with a same port-priority destination experience similar latency within specific time-window, which is similar to the packet service provided by an Output Queue switch architecture. In one embodiment, all input ports that send traffic to same output port-priority receive bandwidth which is proportional to their bandwidth demand divided by total bandwidth. Prior approaches that emulate the performance of an OQ switch architecture require complex and time-consuming scheduling determinations and do not scale. Independently determining the order for sending packets from the VOQs associated with each particular OQ provides a scalable and implementable system with quasi-Output Queue behavior.

Abstract: The throughput of the memory system is improved where data in a data stream is cryptographically processed by a circuit without involving intimately any controller. The data stream is preferably controlled so that it has a selected data source among a plurality of sources and a selected destination among a plurality of destinations, all without involving the controller. The cryptographic circuit may preferably be configured to enable the processing of multiple pages, selection of one or more cryptographic algorithms among a plurality of algorithms to encryption and/or decryption without involving a controller, and to process data cryptographically in multiple successive stages without involvement of the controller. For a memory system cryptographically processing data from multiple data streams in an interleaved manner, when a session is interrupted, security configuration information may be lost so that it may become impossible to continue the process when the session is resumed.

Abstract: Some demonstrative embodiments of the invention include a method, device and/or system to encrypt and/or decrypt data. In one demonstrative embodiment, the device may include, for example, a storage; and an encryption/decryption module to: receive externally-encrypted data to be stored in the storage, wherein the externally-encrypted data is encrypted using an external key; decrypt the externally-encrypted data using the external key to generate decrypted data; and encrypt the decrypted data using a securely maintained internal key to generate internally-encrypted data. Other embodiments are described and claimed.

Abstract: The throughput of the memory system is improved where data in a data stream is cryptographically processed by a circuit without involving intimately any controller. The data stream is preferably controlled so that it has a selected data source among a plurality of sources and a selected destination among a plurality of destinations, all without involving the controller. The cryptographic circuit may preferably be configured to enable the processing of multiple pages, selection of one or more cryptographic algorithms among a plurality of algorithms to encryption and/or decryption without involving a controller, and to process data cryptographically in multiple successive stages without involvement of the controller. For a memory system cryptographically processing data from multiple data streams in an interleaved manner, when a session is interrupted, security configuration information may be lost so that it may become impossible to continue the process when the session is resumed.

Abstract: Embodiments of the present invention provide a method, apparatus and system of securing an operating system. The apparatus, according to some demonstrative embodiments of the invention, may include a memory access controller to receive from a processor a program counter representing a requested address of a memory to be accessed by the processor during a kernel mode of operation, and to selectively enable the processor to access the requested address based on a comparison between the requested address and one or more allowable addresses. Other embodiments are described and claimed.