Patents by Inventor Aviran Kadosh
Aviran Kadosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9672239Abstract: A TCAM database is partitioned into a plurality of sections. A set of rules to be stored in the TCAM database is analyzed to identify respective subsets of rules that match respective possible bit value combinations corresponding to a subset of bits in the rules, and to identify, in the subsets of rules, two or more subsets that share one or more rules. Then, it is determined whether two or more subsets that include shared rules can be written to a same section in the TCAM database, without exceeding a maximum number of rules that can be written to the same section, when one or more duplicates of one the the shared rules is omitted from the TCAM database. When it is determined that two or more subsets can be written to the same section, the two or more subsets are written to the same section in the TCAM database.Type: GrantFiled: October 16, 2013Date of Patent: June 6, 2017Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Ori Rottenstreich, Aviran Kadosh, Carmi Arad, Yoram Revah
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Patent number: 9674102Abstract: Header information is extracted from a received packet by a data path portion of a network device. The data path portion is configured to buffer a data portion of received packets until the received packets are ready for transmission from the network device. The data path portion determines a first classification identifier for the received packet based on the header information. The data path portion determines a congestion state of the data path portion. The congestion state indicates a received packet rate of the first data path portion that exceeds a packet handling rate of a control path portion of the network device. The data path portion discards the first packet if the congestion state meets a discard threshold associated with the first classification identifier.Type: GrantFiled: December 18, 2014Date of Patent: June 6, 2017Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Gil Levy, Aviran Kadosh
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Patent number: 9571380Abstract: A packet is received at a packet processing element, among a plurality of like packet processing elements, of a network device, and request specifying a processing operation to be performed with respect to the packet by an accelerator engine functionally different from the plurality of like packet processing elements is generated by the packet processing element. The request is transmitted to an interconnect network that includes a plurality of interconnect units arranged in stages. A path through the interconnect network is selected among a plurality of candidate paths, wherein no path of the candidate paths includes multiple interconnect units within a same stage of the interconnect network. The request is then transmitted via the determined path to a particular accelerator engine among multiple candidate accelerator engines configured to perform the processing operation. The processing operation is then performed by the particular accelerator engine.Type: GrantFiled: September 10, 2014Date of Patent: February 14, 2017Assignee: Marvell World Trade Ltd.Inventors: Aviran Kadosh, Rami Zemach
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Patent number: 9509639Abstract: A switching device comprises a plurality of switch cores, each switch core having a plurality of ports associated with the switch core. A first switch core is configured to perform ingress processing of a data frame to determine a target port via which the data frame is to be transmitted. If the target port is associated with the first switch core, the first switch core performs egress processing on the data frame and directs the data frame to the target port. If the target port is associated with a second switch core, the data frame is directed to the second switch core at which egress processing on the data frame is performed, including directing the data frame to the target port.Type: GrantFiled: November 9, 2015Date of Patent: November 29, 2016Assignee: MARVELL ISRAEL (M.I.S.L) LTD.Inventors: Aviran Kadosh, Nafea Bshara
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Patent number: 9465619Abstract: Systems and methods are provided for a multi-core processor for processing different types of data units. A system includes a classifier configured to classify incoming data units into different type data units. A plurality of processing cores are selectably configurable into plural processing pipelines, respective processing pipelines including connected processing cores, ones of the processing cores being selectably programmed to execute a respective processing operation on a received incoming data unit, different ones of the processing pipelines defined by a selectable number of processing cores. A distributor is configured to distribute the different types of data units to one of the pipelines among the plural pipelines at least as a function of the classified type of the data units and the programmed processing operations of processing cores in the pipelines.Type: GrantFiled: November 26, 2013Date of Patent: October 11, 2016Assignee: MARVELL ISRAEL (M.I.S.L) LTD.Inventors: Ori Rottenstreich, Yoram Revah, Aviran Kadosh
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Patent number: 9455918Abstract: A forwarding system includes a first processor coupled to connecting devices using a plurality of uplinks, and a second processor coupled to the connecting devices using a plurality of downlinks. The first processor includes, in a memory, one or more queues each corresponding to the second processor, a priority, and/or to a packet cast type (e.g., unicast or multicast). The first processor is configured to select a particular queue, select a particular uplink based on a comparison of measurements corresponding to respective loads of the plurality of uplinks, and cause a fragment or the entirety of a packet in the particular queue to be forwarded to the second processing device using the selected uplink and corresponding connecting device. The second processor is configured to reassemble the packet, reorder the packet into a flow, and forward the packet from the forwarding system.Type: GrantFiled: September 29, 2014Date of Patent: September 27, 2016Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Yoram Revah, Aviran Kadosh
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Patent number: 9407460Abstract: In a method for processing network packets, a network packet is received at an ingress port. After at least a first portion of the network packet has been received, but before the network packet has been completely received, a first data structure representing the network packet is generated based on the first portion, the first data structure is processed, and the network packet begins to be selectively forwarded to a first one or more egress ports, or selectively not forwarded to any egress port, responsively to processing the first data structure. A second data structure representing the network packet is generated and, after the network packet has been completely received, the second data structure is processed, and the network packet is selectively forwarded to a second one or more egress ports, different from the first one or more egress ports, responsively to processing the second data structure.Type: GrantFiled: March 20, 2014Date of Patent: August 2, 2016Assignee: MARVELL WORLD TRADE LTD.Inventors: Shira Turgeman, Gil Levy, Aviran Kadosh
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Patent number: 9407461Abstract: In a method for processing network packets, a network packet is received at an ingress port. Before the network packet has been completely received at the ingress port, a first data structure representing the network packet is generated based on a received first portion of the network packet, and the first data structure is processed at a packet processor of the network device. Processing the first data structure includes making a forwarding decision for the network packet. A second data structure representing the network packet is generated and, after the network packet has been completely received at the ingress port, at least one or more non-forwarding operations are performed with respect to the network packet using at least the second data structure.Type: GrantFiled: March 20, 2014Date of Patent: August 2, 2016Assignee: MARVELL WORLD TRADE LTD.Inventors: Shira Turgeman, Gil Levy, Aviran Kadosh
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Patent number: 9237100Abstract: A method for load balancing in a communication network having a plurality of link aggregate groups includes receiving a data unit at a first one of the plurality of network devices associated with a first one of the plurality of link aggregate groups, applying a hashing function to the data unit to generate a first hash value, where the first hash value identifies a communication link in the first one of the plurality of link aggregate groups, receiving the data unit at a second one of the plurality of network devices associated with a second one of the plurality of link aggregate groups, and applying the hashing function to the data unit to generate a second hash value that is distinct from the first value, where the second hash value identifies a communication link in the second one of the plurality of link aggregate groups along which the data unit is to be communicated.Type: GrantFiled: August 6, 2009Date of Patent: January 12, 2016Assignee: MARVELL ISRAEL (M.I.S.L.) LTD.Inventors: Tal Mizrahi, Aviran Kadosh, Denis Krivitski
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Patent number: 9185052Abstract: A switching device comprises a plurality of switch cores, each switch core having a plurality of ports associated with the switch core. A first switch core is configured to perform ingress processing of a data frame. The data frame is then directed to a second switch core that is configured to perform egress processing of the data frame.Type: GrantFiled: January 18, 2013Date of Patent: November 10, 2015Assignees: Marvell International Ltd., Marvell Israel (M.I.S.L.) Ltd.Inventors: Aviran Kadosh, Nafea Bishara
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Patent number: 9143448Abstract: Data units that are fragments of a larger data unit are received at a network device. A first received fragment of the larger data unit is processed to determine a port of the network device via which the larger data unit is to be transmitted based on a first received fragment of the larger data unit and prior to receiving all of the fragments of the larger data unit. After processing the first received fragment, processing of second received fragments for the purpose of determining the port of the network device via which the larger data unit is to be transmitted is skipped. The larger data unit is reassembled from all of the fragments of the larger data unit after determination of the port of the network device via which the larger data unit is to be transmitted. The larger data unit is forwarded to the port for transmission.Type: GrantFiled: May 30, 2014Date of Patent: September 22, 2015Assignee: MARVELL ISRAEL (M.I.S.L.) LTD.Inventors: Aviran Kadosh, Denis Krivitski
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Patent number: 9112818Abstract: In a method for processing packets, a storage region for a packet is determined based on a queue with which the packet is associated. The storage region includes a committed area reserved for storage of packets associated with the queue, and an area that is shared by multiple queues for packet storage. A first part of the packet is stored in the committed area, a second part is stored in the shared area, and both parts are accounted for. A network device for processing packets comprises a plurality of queues and a storage area including a committed area and a shared area. The network device further comprises a packet queuing engine configured to store a first part of a packet in the committed area, store a second part of the packet in the shared area, and account for the storage of the first and the second parts of the packet.Type: GrantFiled: February 7, 2011Date of Patent: August 18, 2015Assignee: Marvell Isreal (M.I.S.L) Ltd.Inventors: Carmi Arad, Aviran Kadosh
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Publication number: 20150172198Abstract: Header information is extracted from a received packet by a data path portion of a network device. The data path portion is configured to buffer a data portion of received packets until the received packets are ready for transmission from the network device. The data path portion determines a first classification identifier for the received packet based on the header information. The data path portion determines a congestion state of the data path portion. The congestion state indicates a received packet rate of the first data path portion that exceeds a packet handling rate of a control path portion of the network device. The data path portion discards the first packet if the congestion state meets a discard threshold associated with the first classification identifier.Type: ApplicationFiled: December 18, 2014Publication date: June 18, 2015Inventors: Gil LEVY, Aviran KADOSH
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Patent number: 9035678Abstract: A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.Type: GrantFiled: July 10, 2013Date of Patent: May 19, 2015Assignee: Broadcom CorporationInventors: Aviran Kadosh, Golan Schzukin
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Publication number: 20150071079Abstract: A packet is received at a packet processing element, among a plurality of like packet processing elements, of a network device, and request specifying a processing operation to be performed with respect to the packet by an accelerator engine functionally different from the plurality of like packet processing elements is generated by the packet processing element. The request is transmitted to an interconnect network that includes a plurality of interconnect units arranged in stages. A path through the interconnect network is selected among a plurality of candidate paths, wherein no path of the candidate paths includes multiple interconnect units within a same stage of the interconnect network. The request is then transmitted via the determined path to a particular accelerator engine among multiple candidate accelerator engines configured to perform the processing operation. The processing operation is then performed by the particular accelerator engine.Type: ApplicationFiled: September 10, 2014Publication date: March 12, 2015Inventors: Aviran KADOSH, Rami ZEMACH
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Patent number: 8848728Abstract: A forwarding system includes a first processor coupled to connecting devices using a plurality of uplinks, and a second processor coupled to the connecting devices using a plurality of downlinks. The first processor includes, in a memory, one or more queues each corresponding to the second processor, a priority, and/or to a packet cast type (e.g., unicast or multicast). The first processor is configured to select a particular queue, select a particular uplink based on a comparison of measurements corresponding to respective loads of the plurality of uplinks, and cause a fragment or the entirety of a packet in the particular queue to be forwarded to the second processing device using the selected uplink and corresponding connecting device. The second processor is configured to reassemble the packet, reorder the packet into a flow, and forward the packet from the forwarding system.Type: GrantFiled: April 6, 2011Date of Patent: September 30, 2014Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Yoram Revah, Aviran Kadosh
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Publication number: 20140286351Abstract: In a method for processing network packets, a network packet is received at an ingress port. After at least a first portion of the network packet has been received, but before the network packet has been completely received, a first data structure representing the network packet is generated based on the first portion, the first data structure is processed, and the network packet begins to be selectively forwarded to a first one or more egress ports, or selectively not forwarded to any egress port, responsively to processing the first data structure. A second data structure representing the network packet is generated and, after the network packet has been completely received, the second data structure is processed, and the network packet is selectively forwarded to a second one or more egress ports, different from the first one or more egress ports, responsively to processing the second data structure.Type: ApplicationFiled: March 20, 2014Publication date: September 25, 2014Applicant: MARVELL WORLD TRADE LTD.Inventors: Shira Turgeman, Gil Levy, Aviran Kadosh
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Publication number: 20140286352Abstract: In a method for processing network packets, a network packet is received at an ingress port. Before the network packet has been completely received at the ingress port, a first data structure representing the network packet is generated based on a received first portion of the network packet, and the first data structure is processed at a packet processor of the network device. Processing the first data structure includes making a forwarding decision for the network packet. A second data structure representing the network packet is generated and, after the network packet has been completely received at the ingress port, at least one or more non-forwarding operations are performed with respect to the network packet using at least the second data structure.Type: ApplicationFiled: March 20, 2014Publication date: September 25, 2014Applicant: MARVELL WORLD TRADE LTD.Inventors: Shira Turgeman, Gil Levy, Aviran Kadosh
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Patent number: 8743907Abstract: An apparatus includes a receive port unit, a forwarding engine, a transmit port unit, and a reassembly unit. In an embodiment, the packet reassembly unit examines headers in received fragments of a data unit and using the headers to reassemble the data unit, wherein the headers correspond to a protocol layer above an IP-layer. In another embodiment, the packet reassembly unit is located downstream from the forwarding engine in a packet forwarding pipeline, and the forwarding engine skips processing fragments received subsequent to a first received fragment.Type: GrantFiled: January 26, 2009Date of Patent: June 3, 2014Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Aviran Kadosh, Denis Krivitski
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Publication number: 20140015567Abstract: A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.Type: ApplicationFiled: July 10, 2013Publication date: January 16, 2014Inventors: Aviran Kadosh, Golan Schzukin