Patents by Inventor Avraham Ayzenfeld
Avraham Ayzenfeld has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916802Abstract: A credit-based flow control system can utilize speculative credit. If an agent has not received a credit return from a downstream agent for a given period of time, the agent can return speculative credit to an upstream agent. This way, even if the agent is not currently capable of performing operations represented by the speculative credit, the upstream agent can be enabled to proceed with operations.Type: GrantFiled: March 31, 2022Date of Patent: February 27, 2024Assignee: International Business Machines CorporationInventors: Giora Biran, Amit Shay, Avraham Ayzenfeld
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Publication number: 20230318984Abstract: A credit-based flow control system can utilize speculative credit. If an agent has not received a credit return from a downstream agent for a given period of time, the agent can return speculative credit to an upstream agent. This way, even if the agent is not currently capable of performing operations represented by the speculative credit, the upstream agent can be enabled to proceed with operations.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Giora Biran, Amit Shay, Avraham Ayzenfeld
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Publication number: 20230273824Abstract: A computer-implemented method, according to one approach, is for establishing coherent analysis across distributed locations. The computer-implemented method includes: processing messages at an initiator location. In response to detecting a query indicator set on one of the messages: an inspection resource is allocated from a pool of available inspection resources to collect initial information associated with the processing of the message having the set query indicator. Moreover, the message is sent to a receiver location with the set query indicator for processing and collecting supplemental information associated with the processing of the message at the receiver location. The initial and supplemental information is eventually collected, and the collected information is processed for determining performance characteristics of the processing of the message at the initiator and receiver locations.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Giora Biran, Amit Shay, Avraham Ayzenfeld
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Patent number: 11474821Abstract: In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.Type: GrantFiled: May 12, 2021Date of Patent: October 18, 2022Assignee: International Business Machines CorporationInventors: Amir Turi, Avraham Ayzenfeld, Gilad Shimon Merran, Yanai Danan, Amit Shay, Yossi Shapira, Yair Fried, Oren Ben Gigi, Omri Rafaeli
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Patent number: 11379228Abstract: An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.Type: GrantFiled: October 16, 2019Date of Patent: July 5, 2022Assignee: International Business Machines CorporationInventors: Avraham Ayzenfeld, Lee E. Eisen, Brian W. Curran, Christian Jacobi
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Patent number: 11144367Abstract: Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.Type: GrantFiled: February 8, 2019Date of Patent: October 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard Joseph Branciforte, Gregory William Alexander, Avraham Ayzenfeld, Edward Thomas Malley, Jonathan Ting Hsieh, Gregory Miaskovsky
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Publication number: 20200257572Abstract: Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.Type: ApplicationFiled: February 8, 2019Publication date: August 13, 2020Inventors: RICHARD JOSEPH BRANCIFORTE, GREGORY WILLIAM ALEXANDER, AVRAHAM AYZENFELD, EDWARD THOMAS MALLEY, JONATHAN TING HSIEH, GREGORY MIASKOVSKY
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Patent number: 10678549Abstract: Examples of techniques for executing instructions out of order are described herein. An example computer-implemented method includes receiving, via a processor, a plurality of instructions to be executed. The method includes sending, via the processor, an instruction to a minimal dependency queue in response to detecting the instruction includes a minimally dependent instruction. The method also includes selecting, via the processor, an instruction from a set of instructions that are eligible to be executed based on a scheme. The method further includes executing, via the processor, the instruction.Type: GrantFiled: November 28, 2017Date of Patent: June 9, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Avraham Ayzenfeld, Eyal Naor, Amir Turi
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Publication number: 20200089493Abstract: An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.Type: ApplicationFiled: October 16, 2019Publication date: March 19, 2020Inventors: Avraham Ayzenfeld, Lee E. Eisen, Brian W. Curran, Christian Jacobi
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Patent number: 10514911Abstract: Examples of techniques for designing processors are described herein. In one example, a design structure can be tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure can include a logic to determine whether a received instruction is an updating fixed point instruction or a non-updating fixed point instruction. The design structure can include a first arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be an updating fixed point instruction and store an update value in a general register. The design structure can include a second arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be a non-updating fixed point instruction.Type: GrantFiled: November 26, 2014Date of Patent: December 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Avraham Ayzenfeld, Lee E. Eisen, Brian W. Curran, Christian Jacobi
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Patent number: 10503503Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction.Type: GrantFiled: September 25, 2015Date of Patent: December 10, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Avraham Ayzenfeld, Lee E. Eisen, Brian W. Curran, Christian Jacobi
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Publication number: 20190310856Abstract: Embodiments of the present invention disclose a method, a computer program product, and a computer system for system for executing instructions, comprising a processor to detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. In addition, the processor can also execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. Furthermore, the processor can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.Type: ApplicationFiled: April 9, 2018Publication date: October 10, 2019Inventors: Avraham Ayzenfeld, AMIR TURI, EYAL NAOR, Ido Rozenberg
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Publication number: 20190163481Abstract: Examples of techniques for executing instructions out of order are described herein. An example computer-implemented method includes receiving, via a processor, a plurality of instructions to be executed. The method includes sending, via the processor, an instruction to a minimal dependency queue in response to detecting the instruction includes a minimally dependent instruction. The method also includes selecting, via the processor, an instruction from a set of instructions that are eligible to be executed based on a scheme. The method further includes executing, via the processor, the instruction.Type: ApplicationFiled: November 28, 2017Publication date: May 30, 2019Inventors: AVRAHAM AYZENFELD, EYAL NAOR, AMIR TURI
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Patent number: 9552312Abstract: A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result.Type: GrantFiled: March 14, 2014Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Avraham Ayzenfeld, Emmanuel Elder, Ilya Granovsky
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Publication number: 20160147530Abstract: Examples of techniques for designing processors are described herein. In one example, a design structure can be tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure can include a logic to determine whether a received instruction is an updating fixed point instruction or a non-updating fixed point instruction. The design structure can include a first arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be an updating fixed point instruction and store an update value in a general register. The design structure can include a second arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be a non-updating fixed point instruction.Type: ApplicationFiled: November 26, 2014Publication date: May 26, 2016Inventors: Avraham Ayzenfeld, Lee E. Eisen, Brian W. Curran, Christian Jacobi
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Publication number: 20160147531Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction.Type: ApplicationFiled: September 25, 2015Publication date: May 26, 2016Inventors: Avraham Ayzenfeld, Lee E. Eisen, Brian W. Curran, Christian Jacobi
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Patent number: 8918568Abstract: An apparatus, including a first multiple of virtual function clusters positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, each of the clusters comprising at least one virtual function, and a second multiple of physical functions positioned on the PCIe configuration space. The apparatus also includes an extended virtual function shell positioned on the PCIe configuration space and configured to select one of the physical functions, to select one of the available virtual function clusters and to associate the selected virtual function cluster with the selected the physical function.Type: GrantFiled: May 6, 2011Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Avraham Ayzenfeld, Emmanuel Elder, Ilya Granovsky
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Publication number: 20140201419Abstract: A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result.Type: ApplicationFiled: March 14, 2014Publication date: July 17, 2014Applicant: International Business Machines CorporationInventors: Avraham Ayzenfeld, Emmanuel Elder, Ilya Granovsky
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Patent number: 8751713Abstract: A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result.Type: GrantFiled: May 6, 2011Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Avraham Ayzenfeld, Emmanuel Elder, Ilya Granovsky
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Publication number: 20120284437Abstract: An apparatus, including a first multiple of virtual function clusters positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, each of the clusters comprising at least one virtual function, and a second multiple of physical functions positioned on the PCIe configuration space. The apparatus also includes an extended virtual function shell positioned on the PCIe configuration space and configured to select one of the physical functions, to select one of the available virtual function clusters and to associate the selected virtual function cluster with the selected the physical function.Type: ApplicationFiled: May 6, 2011Publication date: November 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Avraham Ayzenfeld, Emmanuel Elder, Ilya Granovsky