Patents by Inventor Avtar K. Saini

Avtar K. Saini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit including a latching unit for holding instructions during execution for re-execution following exception handling
    Patent number: 5421021
    Abstract: A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstrictions includes an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: May 30, 1995
    Assignee: Intel Corporation
    Inventor: Avtar K. Saini
  • System for handling exceptions occurring during parallel execution of microinstructions
    Patent number: 5416912
    Abstract: A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstructions includes an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means.
    Type: Grant
    Filed: August 11, 1993
    Date of Patent: May 16, 1995
    Assignee: Intel Corporation
    Inventor: Avtar K. Saini
  • System for re-execution of instruction after exception handling in first processing path while concurrently executing instructions in second processing path
    Patent number: 5375212
    Abstract: A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstructions includes an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: December 20, 1994
    Assignee: Intel Corporation
    Inventor: Avtar K. Saini