Abstract: A method for performing consecutive instructions to push data onto a stack in memory in a digital computer is described. During a first clock cycle, an instruction is decoded requiring a stack push operation. A control indicator is also generated calling for a stack push operation. During a phase one of a second clock cycle, (a) a stack pointer value stored in a selected stack pointer register is written onto a first bus, the selected stack pointer register being one of either the first stack pointer register or the second stack point register, and (b) the stack pointer value stored in the selected stack pointer register is written into an input latch of a stack pointer adder.

Abstract: A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstructions include an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means.

Abstract: A method nad circuitry for multiplication in a digital system is described. The circuitry includes a partial product generator, a carry-save adder, a sum latch, a carry latch, an adder, a latch, circuitry for truncating, and coupling circuitry. A method and circuitry for optimizing a speed of a subsequent multiplication in a digital system is described. Circuitry for optimizing multiplication clock cycles in a digital system is described.

Abstract: An apparatus and method for converting the format of the exponent portion of a biased floating point number in a microprocessor is disclosed. The present invention allows a conversion to be performed as the data is being loaded. Decoding circuitry first determines when floating point data is about to be loaded. A constant, which corresponds to the type of conversion to be performed, is then generated from a ROM. The data and constant are added and the result, representing the converted exponent is stored in an exponent resister within one clock period.