Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.

Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.

Abstract: An electronic device may be provided with a housing such as a metal housing in which a display is mounted. Control circuitry in the electronic device such as a system-on-chip integrated circuit may produce image data. A display driver integrated circuit may receive the image data from the system-on-chip integrated circuit and may display the image data on the display. In the absence of electrostatic discharge, the display driver integrated circuit may operate normally and may generate a heartbeat signal. When disrupted due to electrostatic discharge, the display driver circuitry may cease production of the heartbeat signal. The system-on-chip integrated circuit can implement a watchdog timer. If the watchdog timer times out because the heartbeat signal is not received within a timeout period, the system-on-chip integrated circuit may reset the display.