Patents by Inventor Axel FANGET

Axel FANGET has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12282054
    Abstract: A system for characterizing a transistor circuit which has a local minimum in its transfer characteristic by finding its local minimum. The system comprises: a bias voltage generator for generating a toggling signal; a multiplier configured for multiplying an electrical signal which is a function of the drain source current of the transistor circuit, with a waveform alternating between two predefined values synchronously with the toggling signal; a first integrator configured for integrating the electrical signal from the multiplier, and wherein if more integrators are present, linear combinations of output signals of the integrators are provided to the further integrators; a summator configured for summing the toggling signal and an integration signal and configured for outputting the sum to the gate of the transistor circuit.
    Type: Grant
    Filed: November 2, 2023
    Date of Patent: April 22, 2025
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Francois Piette, Cliff De Locht, Axel Fanget, Andreas Ott, Andreas Laute, Thomas Freitag
  • Publication number: 20240159820
    Abstract: A system for characterizing a transistor circuit which has a local minimum in its transfer characteristic by finding its local minimum. The system comprises: a bias voltage generator for generating a toggling signal; a multiplier configured for multiplying an electrical signal which is a function of the drain source current of the transistor circuit, with a waveform alternating between two predefined values synchronously with the toggling signal; a first integrator configured for integrating the electrical signal from the multiplier, and wherein if more integrators are present, linear combinations of output signals of the integrators are provided to the further integrators; a summator configured for summing the toggling signal and an integration signal and configured for outputting the sum to the gate of the transistor circuit.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 16, 2024
    Inventors: Francois PIETTE, Cliff DE LOCHT, Axel FANGET, Andreas OTT, Andreas LAUTE, Thomas FREITAG