Patents by Inventor Aya Minami

Aya Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11681873
    Abstract: Methods, apparatus, and products for creating an executable process from a text description written in a natural language in accordance with the present invention are described. A set of propositions is extracted from a text document written in a natural language. Based on the set extracted of propositions, a set of formulas is extracted from the text document. A state transition graph comprising a set of proposition value determination paths constrained by the set of formulas is then created. The state transition graph is translated into a software application.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: June 20, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takeshi Inagaki, Aya Minami
  • Patent number: 11663519
    Abstract: A computer-implemented method according to one embodiment includes receiving a single instance of training data, simplifying the single instance of training data to create a single instance of simplified training data, generating a plurality of training data variants, based on the single instance of simplified training data, and training a machine learning model, utilizing the plurality of training data variants.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Inagaki, Aya Minami
  • Publication number: 20210073330
    Abstract: Methods, apparatus, and products for creating an executable process from a text description written in a natural language in accordance with the present invention are described. A set of propositions is extracted from a text document written in a natural language. Based on the set extracted of propositions, a set of formulas is extracted from the text document. A state transition graph comprising a set of proposition value determination paths constrained by the set of formulas is then created. The state transition graph is translated into a software application.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventors: TAKESHI INAGAKI, AYA MINAMI
  • Publication number: 20200342312
    Abstract: A computer-implemented method according to one embodiment includes applying a first instance of input to a first model within a tree structure, activating a second model within the tree structure, based on an identification of a first topic within the first instance of input by the first model, applying a second instance of input to the first model and the second model, activating a third model within the tree structure, based on an identification of a second topic within the second instance of input by the second model, applying a third instance of input to the first model, the second model, and the third model, and outputting, by the third model, an identification of a third topic, utilizing the third instance of input.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: Takeshi Inagaki, Aya Minami
  • Publication number: 20200342354
    Abstract: A computer-implemented method according to one embodiment includes receiving a single instance of training data, simplifying the single instance of training data to create a single instance of simplified training data, generating a plurality of training data variants, based on the single instance of simplified training data, and training a machine learning model, utilizing the plurality of training data variants.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: Takeshi Inagaki, Aya Minami
  • Patent number: 8918590
    Abstract: The present invention provides a ring bus type multicore system including one memory, a main memory controller for connecting the memory to a ring bus; and multiple cores connected in the shape of the ring bus, wherein each of the cores further includes a cache interface and a cache controller for controlling or managing the interface, and the cache controller of each of the cores connected in the shape of the ring bus executes a step of snooping data on the request through the cache interface; and when the cache of the core holds the data, a step of controlling the core to receive the request and return the data to the requester core, or, when the cache of the core does not hold the data, the main memory controller executes a step of reading the data from the memory and sending the data to the requester core.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Aya Minami, Yohichi Miwa
  • Patent number: 8364939
    Abstract: Disclosed is a system including: a calibration executing unit that performs a calibration on hardware during the system startup so as to allow the system to properly operate; and a correction data retaining unit that retains a piece of correction information in association with an environmental condition during the calibration, the correction information indicating a setting for the hardware calibrated by the calibration executing unit. If the correction data retaining unit retains the correction information associated with an environmental condition equivalent to the environmental condition at a time when the system is started up, the calibration executing unit performs the hardware setting on the basis of the retained correction information instead of calibrating the hardware.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Aya Minami, Yohichi Miwa
  • Publication number: 20120305659
    Abstract: A highly convenient radio frequency integrated circuit that can be used at a plurality of different frequency bands, and which can perform communications at the different frequency bands so that data at different frequency bands can be read and a restriction can be imposed on the reading and writing of information. An IC module in a radio frequency integrated circuit includes a plurality of memories; a read-write unit for performing a process of reading data from, and writing data into, the memories; and a selector for receiving an electric signal outputted from an antenna that has received a radio signal.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yohichi Miwa, Aya Minami
  • Patent number: 8285242
    Abstract: A highly convenient radio frequency integrated circuit that can be used at a plurality of different frequency bands, and which can perform communications at the different frequency bands so that data at different frequency bands can be read and a restriction can be imposed on the reading and writing of information. An IC module in a radio frequency integrated circuit includes a plurality of memories; a read-write unit for performing a process of reading data from, and writing data into, the memories; and a selector for receiving an electric signal outputted from an antenna that has received a radio signal.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: October 9, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yohichi Miwa, Aya Minami
  • Publication number: 20120151152
    Abstract: The present invention provides a ring bus type multicore system including one memory, a main memory controller for connecting the memory to a ring bus; and multiple cores connected in the shape of the ring bus, wherein each of the cores further includes a cache interface and a cache controller for controlling or managing the interface, and the cache controller of each of the cores connected in the shape of the ring bus executes a step of snooping data on the request through the cache interface; and when the cache of the core holds the data, a step of controlling the core to receive the request and return the data to the requester core, or, when the cache of the core does not hold the data, the main memory controller executes a step of reading the data from the memory and sending the data to the requester core.
    Type: Application
    Filed: December 5, 2011
    Publication date: June 14, 2012
    Applicant: International Business Machines Corporation
    Inventors: Aya Minami, Yohichi Miwa
  • Patent number: 8010771
    Abstract: The invention provides a communication system including a plurality of communication nodes respectively arranged at predetermined lattice points in lattice space forming a three-dimensional rectangular solid, a communication link that interconnects communication nodes arranged at adjacent lattice points, and a shortcut link that connects, for at least two faces that are not an end face on the lattice space among faces formed of communication nodes of which any adjacent lattice points do not have communication nodes, a communication node constituting one face and a communication node constituting another face.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Inagaki, Aya Minami, Yohichi Miwa
  • Patent number: 7953368
    Abstract: Included are: a circuit unit having a non-volatile memory; a circuit unit having a volatile memory; a read-write circuit for reading data from, writing data into, the non-volatile memory, and for reading data from, writing data into, the volatile memory; an antenna and an RF amplifier which are first power supply means for receiving a first radio wave, and for supplying power to the circuit unit; and an antenna and an RF amplifier which are second power supply means for receiving a second radio wave whose frequency is different from that of the first radio wave, and for supplying power to the circuit unit.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Yohichi Miwa, Aya Minami
  • Patent number: 7782621
    Abstract: A circuit module includes: a thermally conductive board forming a part of a housing; a circuit board disposed above the thermally conductive board; a semiconductor chip connected to a plurality of electrode pads on a upper surface of the circuit board through solder; a heat sink connected to a upper surface of the semiconductor chip; a thermally conductive member thermally connecting the thermally conductive board to the semiconductor chip; and a plurality of fasteners passing through the thickness of the circuit board in an area surrounding the semiconductor chip to attach the heat sink to the thermally conductive board.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Takuji Matsushiba, Aya Minami, Yohichi Miwa, Taichiroh Nomura, Kenji Tsuboi, Takeshi Wagatsuma, Masatake Yamamoto
  • Publication number: 20100211768
    Abstract: Disclosed is a system including: a calibration executing unit that performs a calibration on hardware during the system startup so as to allow the system to properly operate; and a correction data retaining unit that retains a piece of correction information in association with an environmental condition during the calibration, the correction information indicating a setting for the hardware calibrated by the calibration executing unit. If the correction data retaining unit retains the correction information associated with an environmental condition equivalent to the environmental condition at a time when the system is started up, the calibration executing unit performs the hardware setting on the basis of the retained correction information instead of calibrating the hardware.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 19, 2010
    Applicant: International Business Machines Corporation
    Inventors: Aya Minami, Yohichi Miwa
  • Publication number: 20090116194
    Abstract: A circuit module includes: a thermally conductive board forming a part of a housing; a circuit board disposed above the thermally conductive board; a semiconductor chip connected to a plurality of electrode pads on a upper surface of the circuit board through solder; a heat sink connected to a upper surface of the semiconductor chip; a thermally conductive member thermally connecting the thermally conductive board to the semiconductor chip; and a plurality of fasteners passing through the thickness of the circuit board in an area surrounding the semiconductor chip to attach the heat sink to the thermally conductive board.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 7, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takuji Matsushiba, Aya Minami, Yohichi Miwa, Taichiroh Nomura, Kenji Tsuboi, Takeshi Wagatsuma, Masatake Yamamoto
  • Patent number: 7523008
    Abstract: This is an embodiment for enabling calibration of the bus interfacing cell processors and I/O Controllers in a multi-cell system without rebooting the system in response to a change in the environment temperature. This is accomplished by periodically checking the intake temperature. If the temperature rise is less than a predefined threshold, no action is taken. If the temperature rise is more than a predefined threshold, external interfaces are disabled, cell operations are halted and calibration is performed. Once the calibration is completed, cell operations are resumed and external interfaces are re-enabled.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Yohichi Miwa, Aya Minami, Toshiyuki Sanuki
  • Patent number: 7506176
    Abstract: An embodiment describes a method of implementing higher level and more robust encryption by using a multi-core processor. The clear text is segmented into text segments based on predefined segment lengths by master processor. Text segments are sent to processing elements which in turn encrypted and encrypted segments are sent back to master processor which is aggregated into encrypted text. To decrypt the text, encrypted text is split into encrypted segments per predefined lengths by master processor and sent to processing elements to be decrypted. The resulted plain text segments are sent back to master processor which is aggregated into original plain text.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: March 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Yohichi Miwa, Aya Minami
  • Publication number: 20070294567
    Abstract: Member disks of a hard disk drive array are replaced with spare disks. First, a member disk of an array of member disks is replaced with a spare disk. The reliability factor of the member disk is lower than the reliability factor of the array, and the reliability factor of the spare disk is equal to or higher than the reliability factor of the array. Second, a member disk of an array of member disks is replaced with a spare disk. The reliability factor of the member disk is higher than the reliability factor of the array and is higher than the reliability factor of the spare disk. The reliability of the spare disk is equal to or higher than the reliability factor of the array.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 20, 2007
    Inventors: Hiroyuki Miyoshi, Miwa Yohichi, Aya Minami
  • Publication number: 20070133580
    Abstract: The invention provides a communication system including a plurality of communication nodes respectively arranged at predetermined lattice points in lattice space forming a three-dimensional rectangular solid, a communication link that interconnects communication nodes arranged at adjacent lattice points, and a shortcut link that connects, for at least two faces that are not an end face on the lattice space among faces formed of communication nodes of which any adjacent lattice points do not have communication nodes, a communication node constituting one face and a communication node constituting another face.
    Type: Application
    Filed: December 4, 2006
    Publication date: June 14, 2007
    Inventors: Takeshi Inagaki, Aya Minami, Yohichi Miwa
  • Patent number: 7076607
    Abstract: A system, method, and apparatus are disclosed for storing segmented data and corresponding parity data with modules configured to functionally execute the necessary steps of storing segmented data and corresponding parity data. These modules, in the described embodiments, include a designation module that designates a first set of data, from parity data and a plurality of segmented data, as surplus data and designates the remaining data as primary data. A storage module stores the primary data in main electronic storage devices in a distributed manner and stores a first copy of the surplus data on a first main electronic storage device and a second copy of the surplus data on a second main electronic storage device. An optional auxiliary storage module selectively activates an auxiliary electronic storage device and stores the surplus data on the auxiliary storage device. Beneficially, selective activation of the auxiliary electronic storage conserves power.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: July 11, 2006
    Assignee: International Business Machines Corporation
    Inventors: Yohichi Miwa, Aya Minami, Tsuyoshi Motoki