Patents by Inventor Aya Minami
Aya Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11681873Abstract: Methods, apparatus, and products for creating an executable process from a text description written in a natural language in accordance with the present invention are described. A set of propositions is extracted from a text document written in a natural language. Based on the set extracted of propositions, a set of formulas is extracted from the text document. A state transition graph comprising a set of proposition value determination paths constrained by the set of formulas is then created. The state transition graph is translated into a software application.Type: GrantFiled: September 11, 2019Date of Patent: June 20, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takeshi Inagaki, Aya Minami
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Patent number: 11663519Abstract: A computer-implemented method according to one embodiment includes receiving a single instance of training data, simplifying the single instance of training data to create a single instance of simplified training data, generating a plurality of training data variants, based on the single instance of simplified training data, and training a machine learning model, utilizing the plurality of training data variants.Type: GrantFiled: April 29, 2019Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Takeshi Inagaki, Aya Minami
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Publication number: 20210073330Abstract: Methods, apparatus, and products for creating an executable process from a text description written in a natural language in accordance with the present invention are described. A set of propositions is extracted from a text document written in a natural language. Based on the set extracted of propositions, a set of formulas is extracted from the text document. A state transition graph comprising a set of proposition value determination paths constrained by the set of formulas is then created. The state transition graph is translated into a software application.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Inventors: TAKESHI INAGAKI, AYA MINAMI
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Publication number: 20200342312Abstract: A computer-implemented method according to one embodiment includes applying a first instance of input to a first model within a tree structure, activating a second model within the tree structure, based on an identification of a first topic within the first instance of input by the first model, applying a second instance of input to the first model and the second model, activating a third model within the tree structure, based on an identification of a second topic within the second instance of input by the second model, applying a third instance of input to the first model, the second model, and the third model, and outputting, by the third model, an identification of a third topic, utilizing the third instance of input.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Takeshi Inagaki, Aya Minami
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Publication number: 20200342354Abstract: A computer-implemented method according to one embodiment includes receiving a single instance of training data, simplifying the single instance of training data to create a single instance of simplified training data, generating a plurality of training data variants, based on the single instance of simplified training data, and training a machine learning model, utilizing the plurality of training data variants.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Takeshi Inagaki, Aya Minami
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Patent number: 8918590Abstract: The present invention provides a ring bus type multicore system including one memory, a main memory controller for connecting the memory to a ring bus; and multiple cores connected in the shape of the ring bus, wherein each of the cores further includes a cache interface and a cache controller for controlling or managing the interface, and the cache controller of each of the cores connected in the shape of the ring bus executes a step of snooping data on the request through the cache interface; and when the cache of the core holds the data, a step of controlling the core to receive the request and return the data to the requester core, or, when the cache of the core does not hold the data, the main memory controller executes a step of reading the data from the memory and sending the data to the requester core.Type: GrantFiled: December 5, 2011Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Aya Minami, Yohichi Miwa
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Patent number: 8364939Abstract: Disclosed is a system including: a calibration executing unit that performs a calibration on hardware during the system startup so as to allow the system to properly operate; and a correction data retaining unit that retains a piece of correction information in association with an environmental condition during the calibration, the correction information indicating a setting for the hardware calibrated by the calibration executing unit. If the correction data retaining unit retains the correction information associated with an environmental condition equivalent to the environmental condition at a time when the system is started up, the calibration executing unit performs the hardware setting on the basis of the retained correction information instead of calibrating the hardware.Type: GrantFiled: February 11, 2010Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Aya Minami, Yohichi Miwa
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Publication number: 20120305659Abstract: A highly convenient radio frequency integrated circuit that can be used at a plurality of different frequency bands, and which can perform communications at the different frequency bands so that data at different frequency bands can be read and a restriction can be imposed on the reading and writing of information. An IC module in a radio frequency integrated circuit includes a plurality of memories; a read-write unit for performing a process of reading data from, and writing data into, the memories; and a selector for receiving an electric signal outputted from an antenna that has received a radio signal.Type: ApplicationFiled: August 16, 2012Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yohichi Miwa, Aya Minami
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Patent number: 8285242Abstract: A highly convenient radio frequency integrated circuit that can be used at a plurality of different frequency bands, and which can perform communications at the different frequency bands so that data at different frequency bands can be read and a restriction can be imposed on the reading and writing of information. An IC module in a radio frequency integrated circuit includes a plurality of memories; a read-write unit for performing a process of reading data from, and writing data into, the memories; and a selector for receiving an electric signal outputted from an antenna that has received a radio signal.Type: GrantFiled: September 15, 2005Date of Patent: October 9, 2012Assignee: International Business Machines CorporationInventors: Yohichi Miwa, Aya Minami
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Publication number: 20120151152Abstract: The present invention provides a ring bus type multicore system including one memory, a main memory controller for connecting the memory to a ring bus; and multiple cores connected in the shape of the ring bus, wherein each of the cores further includes a cache interface and a cache controller for controlling or managing the interface, and the cache controller of each of the cores connected in the shape of the ring bus executes a step of snooping data on the request through the cache interface; and when the cache of the core holds the data, a step of controlling the core to receive the request and return the data to the requester core, or, when the cache of the core does not hold the data, the main memory controller executes a step of reading the data from the memory and sending the data to the requester core.Type: ApplicationFiled: December 5, 2011Publication date: June 14, 2012Applicant: International Business Machines CorporationInventors: Aya Minami, Yohichi Miwa
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Patent number: 8010771Abstract: The invention provides a communication system including a plurality of communication nodes respectively arranged at predetermined lattice points in lattice space forming a three-dimensional rectangular solid, a communication link that interconnects communication nodes arranged at adjacent lattice points, and a shortcut link that connects, for at least two faces that are not an end face on the lattice space among faces formed of communication nodes of which any adjacent lattice points do not have communication nodes, a communication node constituting one face and a communication node constituting another face.Type: GrantFiled: December 4, 2006Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Takeshi Inagaki, Aya Minami, Yohichi Miwa
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Patent number: 7953368Abstract: Included are: a circuit unit having a non-volatile memory; a circuit unit having a volatile memory; a read-write circuit for reading data from, writing data into, the non-volatile memory, and for reading data from, writing data into, the volatile memory; an antenna and an RF amplifier which are first power supply means for receiving a first radio wave, and for supplying power to the circuit unit; and an antenna and an RF amplifier which are second power supply means for receiving a second radio wave whose frequency is different from that of the first radio wave, and for supplying power to the circuit unit.Type: GrantFiled: December 14, 2005Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Yohichi Miwa, Aya Minami
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Patent number: 7782621Abstract: A circuit module includes: a thermally conductive board forming a part of a housing; a circuit board disposed above the thermally conductive board; a semiconductor chip connected to a plurality of electrode pads on a upper surface of the circuit board through solder; a heat sink connected to a upper surface of the semiconductor chip; a thermally conductive member thermally connecting the thermally conductive board to the semiconductor chip; and a plurality of fasteners passing through the thickness of the circuit board in an area surrounding the semiconductor chip to attach the heat sink to the thermally conductive board.Type: GrantFiled: November 3, 2008Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: Takuji Matsushiba, Aya Minami, Yohichi Miwa, Taichiroh Nomura, Kenji Tsuboi, Takeshi Wagatsuma, Masatake Yamamoto
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Publication number: 20100211768Abstract: Disclosed is a system including: a calibration executing unit that performs a calibration on hardware during the system startup so as to allow the system to properly operate; and a correction data retaining unit that retains a piece of correction information in association with an environmental condition during the calibration, the correction information indicating a setting for the hardware calibrated by the calibration executing unit. If the correction data retaining unit retains the correction information associated with an environmental condition equivalent to the environmental condition at a time when the system is started up, the calibration executing unit performs the hardware setting on the basis of the retained correction information instead of calibrating the hardware.Type: ApplicationFiled: February 11, 2010Publication date: August 19, 2010Applicant: International Business Machines CorporationInventors: Aya Minami, Yohichi Miwa
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Publication number: 20090116194Abstract: A circuit module includes: a thermally conductive board forming a part of a housing; a circuit board disposed above the thermally conductive board; a semiconductor chip connected to a plurality of electrode pads on a upper surface of the circuit board through solder; a heat sink connected to a upper surface of the semiconductor chip; a thermally conductive member thermally connecting the thermally conductive board to the semiconductor chip; and a plurality of fasteners passing through the thickness of the circuit board in an area surrounding the semiconductor chip to attach the heat sink to the thermally conductive board.Type: ApplicationFiled: November 3, 2008Publication date: May 7, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takuji Matsushiba, Aya Minami, Yohichi Miwa, Taichiroh Nomura, Kenji Tsuboi, Takeshi Wagatsuma, Masatake Yamamoto
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Patent number: 7523008Abstract: This is an embodiment for enabling calibration of the bus interfacing cell processors and I/O Controllers in a multi-cell system without rebooting the system in response to a change in the environment temperature. This is accomplished by periodically checking the intake temperature. If the temperature rise is less than a predefined threshold, no action is taken. If the temperature rise is more than a predefined threshold, external interfaces are disabled, cell operations are halted and calibration is performed. Once the calibration is completed, cell operations are resumed and external interfaces are re-enabled.Type: GrantFiled: March 10, 2008Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Yohichi Miwa, Aya Minami, Toshiyuki Sanuki
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Patent number: 7506176Abstract: An embodiment describes a method of implementing higher level and more robust encryption by using a multi-core processor. The clear text is segmented into text segments based on predefined segment lengths by master processor. Text segments are sent to processing elements which in turn encrypted and encrypted segments are sent back to master processor which is aggregated into encrypted text. To decrypt the text, encrypted text is split into encrypted segments per predefined lengths by master processor and sent to processing elements to be decrypted. The resulted plain text segments are sent back to master processor which is aggregated into original plain text.Type: GrantFiled: March 10, 2008Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Yohichi Miwa, Aya Minami
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Publication number: 20070294567Abstract: Member disks of a hard disk drive array are replaced with spare disks. First, a member disk of an array of member disks is replaced with a spare disk. The reliability factor of the member disk is lower than the reliability factor of the array, and the reliability factor of the spare disk is equal to or higher than the reliability factor of the array. Second, a member disk of an array of member disks is replaced with a spare disk. The reliability factor of the member disk is higher than the reliability factor of the array and is higher than the reliability factor of the spare disk. The reliability of the spare disk is equal to or higher than the reliability factor of the array.Type: ApplicationFiled: June 5, 2006Publication date: December 20, 2007Inventors: Hiroyuki Miyoshi, Miwa Yohichi, Aya Minami
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Publication number: 20070133580Abstract: The invention provides a communication system including a plurality of communication nodes respectively arranged at predetermined lattice points in lattice space forming a three-dimensional rectangular solid, a communication link that interconnects communication nodes arranged at adjacent lattice points, and a shortcut link that connects, for at least two faces that are not an end face on the lattice space among faces formed of communication nodes of which any adjacent lattice points do not have communication nodes, a communication node constituting one face and a communication node constituting another face.Type: ApplicationFiled: December 4, 2006Publication date: June 14, 2007Inventors: Takeshi Inagaki, Aya Minami, Yohichi Miwa
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Patent number: 7076607Abstract: A system, method, and apparatus are disclosed for storing segmented data and corresponding parity data with modules configured to functionally execute the necessary steps of storing segmented data and corresponding parity data. These modules, in the described embodiments, include a designation module that designates a first set of data, from parity data and a plurality of segmented data, as surplus data and designates the remaining data as primary data. A storage module stores the primary data in main electronic storage devices in a distributed manner and stores a first copy of the surplus data on a first main electronic storage device and a second copy of the surplus data on a second main electronic storage device. An optional auxiliary storage module selectively activates an auxiliary electronic storage device and stores the surplus data on the auxiliary storage device. Beneficially, selective activation of the auxiliary electronic storage conserves power.Type: GrantFiled: January 24, 2003Date of Patent: July 11, 2006Assignee: International Business Machines CorporationInventors: Yohichi Miwa, Aya Minami, Tsuyoshi Motoki