Patents by Inventor Aya Miyazaki
Aya Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8018776Abstract: The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.Type: GrantFiled: July 14, 2010Date of Patent: September 13, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Mitsuaki Osame, Aya Miyazaki
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Publication number: 20110216876Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.Type: ApplicationFiled: February 28, 2011Publication date: September 8, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
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Publication number: 20110204424Abstract: An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Ryo ARASAWA, Aya MIYAZAKI, Shigeharu MONOE, Shunpei YAMAZAKI
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Patent number: 7961525Abstract: To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.Type: GrantFiled: June 25, 2009Date of Patent: June 14, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsuaki Osame, Hiroyuki Miyake, Aya Miyazaki, Shunpei Yamazaki
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Patent number: 7952100Abstract: An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.Type: GrantFiled: September 14, 2007Date of Patent: May 31, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Ryo Arasawa, Aya Miyazaki, Shigeharu Monoe, Shunpei Yamazaki
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Publication number: 20100277985Abstract: The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.Type: ApplicationFiled: July 14, 2010Publication date: November 4, 2010Inventors: Hiroyuki Miyake, Mitsuaki Osame, Aya Miyazaki
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Patent number: 7760552Abstract: The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.Type: GrantFiled: March 28, 2007Date of Patent: July 20, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Mitsuaki Osame, Aya Miyazaki
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Patent number: 7755581Abstract: The present invention provides a semiconductor device and its driving method in which amplitude of a data line is decreased to reduce power consumption. In a reset period, a reset transistor and a switch transistor are turned on. In the reset period, an input of a potential from the reset transistor is dominant in a node D, and a selection transistor is turned off when a potential of the node D gets higher than a gate potential of the selection transistor. Thus, even though a potential of the data line changes, a potential of the node G does not change. Since the potential of the data line is not directly written in a gate of a driver transistor, it is possible to separately set an on/off potential to be applied to the gate of the driver transistor and the amplitude of the data line.Type: GrantFiled: April 10, 2006Date of Patent: July 13, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsuaki Osame, Aya Miyazaki
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Patent number: 7737442Abstract: A semiconductor device of the present invention has a first conductive layer, a second conductive layer, an insulating layer which is formed between the first conductive layer and the second conductive layer and which has a contact hole, and a third conductive layer which is connected to the first conductive layer and the second conductive layer and of which at least a part of an end portion is formed inside the contact hole. Near a contact hole where the second conductive layer is connected to the third conductive layer, the third conductive layer does not overlap with the second conductive layer with the first insulating layer interposed therebetween and an end portion of the third conductive layer is not formed over the first insulating layer. This allows suppression of depression and projection of the third conductive layer.Type: GrantFiled: June 27, 2006Date of Patent: June 15, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masayuki Sakakura, Aya Miyazaki
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Publication number: 20100133601Abstract: A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.Type: ApplicationFiled: February 5, 2010Publication date: June 3, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Aya MIYAZAKI, Mitsuaki OSAME, Hiroyuki MIYAKE, Shunpei YAMAZAKI
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Patent number: 7692973Abstract: A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.Type: GrantFiled: March 23, 2007Date of Patent: April 6, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventors: Aya Miyazaki, Mitsuaki Osame, Hiroyuki Miyake, Shunpei Yamazaki
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Publication number: 20090257283Abstract: To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.Type: ApplicationFiled: June 25, 2009Publication date: October 15, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Mitsuaki Osame, Hiroyuki Miyake, Aya Miyazaki, Shunpei Yamazaki
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Patent number: 7554854Abstract: To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.Type: GrantFiled: March 12, 2007Date of Patent: June 30, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsuaki Osame, Hiroyuki Miyake, Aya Miyazaki, Shunpei Yamazaki
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Publication number: 20090079350Abstract: The present invention provides a semiconductor device and its driving method in which amplitude of a data line is decreased to reduce power consumption. In a reset period, a reset transistor and a switch transistor are turned on. In the reset period, an input of a potential from the reset transistor node G is dominant in a node D, and a selection transistor is turned off when a potential of the node D gets higher than a gate potential of the selection transistor. Thus, even though a potential of the data line changes, a potential of the node G does not change. Since the potential of the data line is not directly written in a gate of a driver transistor, it is possible to separately set an on/off potential to be applied to the gate of the driver transistor and the amplitude of the data line.Type: ApplicationFiled: April 10, 2006Publication date: March 26, 2009Inventors: Mitsuaki Osame, Aya Miyazaki
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Patent number: 7450093Abstract: A light emitting device that achieves long life, and which is capable of performing high duty drive, by suppressing initial light emitting element deterioration is provided. Reverse bias application to an EL element (109) is performed one row at a time by forming a reverse bias electric power source line (112) and a reverse bias TFT (108). Reverse bias application can therefore be performed in synchronous with operations for write-in of an image signal, light emission, erasure, and the like. Reverse bias application therefore becomes possible while maintaining a duty equivalent to that of a conventional driving method.Type: GrantFiled: February 1, 2007Date of Patent: November 11, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsuaki Osame, Aya Miyazaki, Yoshifumi Tanada, Keisuke Miyagawa, Satoshi Seo, Shunpei Yamazaki
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Publication number: 20080094343Abstract: If the frequency of a clock signal is increased, the pulse width of a sampling pulse is decreased, and the amount of time for a video signal to be written to a source line is inadequate. Sampling pulses (sam) rise sequentially in synchronization with the rise of a start pulse (SP). As the start pulse (SP) rises, synchronized with the rise of clock signals (CK, CKB), the sampling pulses (sam) fall off sequentially, delayed by half the period of the clock signals (CK, CKB) for every step. As a result, the sampling pulses (sam) with a pulse width longer than one period of the clock signals (CK, CKB) are generated. In a period Ta, a desired video signal (VIDEO) is written to its corresponding source line. In this way, the time for half a period of the clock signal can be secured for writing to the source line.Type: ApplicationFiled: October 4, 2007Publication date: April 24, 2008Inventors: Mitsuaki Osame, Aya Miyazaki
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Publication number: 20080073647Abstract: An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.Type: ApplicationFiled: September 14, 2007Publication date: March 27, 2008Inventors: Ryo Arasawa, Aya Miyazaki, Shigeharu Monoe, Shunpei Yamazaki
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Publication number: 20080029807Abstract: A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.Type: ApplicationFiled: March 23, 2007Publication date: February 7, 2008Inventors: Aya Miyazaki, Mitsuaki Osame, Hiroyuki Miyake, Shunpei Yamazaki
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Publication number: 20070230254Abstract: To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.Type: ApplicationFiled: March 12, 2007Publication date: October 4, 2007Inventors: Mitsuaki Osame, Hiroyuki Miyake, Aya Miyazaki, Shunpei Yamazaki
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Publication number: 20070230249Abstract: The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.Type: ApplicationFiled: March 28, 2007Publication date: October 4, 2007Inventors: Hiroyuki Miyaki, Mitsuaki Osame, Aya Miyazaki