Patents by Inventor Ayad Abdul-Hak

Ayad Abdul-Hak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10692970
    Abstract: A semiconductor device include a semiconductor body with a drain region of a first conductivity type, a drift region of the first conductivity type and having a doping concentration lower than a doping concentration of the drain region, a buffer region of the first conductivity type arranged between the drift region and the drain region, a source region of the first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region and forming a first pn-junction with the source region and a second pn-junction with the drift region, and a charge compensation region of the second conductivity type extending from the body region towards the buffer region. A source metallization is in ohmic contact with the source region. A drain metallization is ohmic contact with the drain region.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Katarzyna Kowalik-Seidl, Ayad Abdul-Hak, Olaf Fiedler, Richard Hensch, Markus Schmitt, Daniel Kai Simon
  • Publication number: 20190148484
    Abstract: A semiconductor device include a semiconductor body with a drain region of a first conductivity type, a drift region of the first conductivity type and having a doping concentration lower than a doping concentration of the drain region, a buffer region of the first conductivity type arranged between the drift region and the drain region, a source region of the first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region and forming a first pn-junction with the source region and a second pn-junction with the drift region, and a charge compensation region of the second conductivity type extending from the body region towards the buffer region. A source metallization is in ohmic contact with the source region. A drain metallization is ohmic contact with the drain region.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 16, 2019
    Inventors: Katarzyna Kowalik-Seidl, Ayad Abdul-Hak, Olaf Fiedler, Richard Hensch, Markus Schmitt, Daniel Kai Simon
  • Patent number: 6794312
    Abstract: A process for producing a nitrided oxide layer on a silicon semiconductor substrate includes introducing a multiplicity of wafers into an atmospheric batch furnace, carrying out an oxidation step at a first predetermined temperature, carrying out a nitriding step at a second predetermined temperature, and carrying out a reoxidation step at a third predetermined temperature. The wafers are then cooled and removed from the atmospheric batch furnace.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: September 21, 2004
    Assignee: Infineon Technologies AG
    Inventors: Ayad Abdul-Hak, Thomas Gaertner, Joerg Schulze
  • Publication number: 20030032307
    Abstract: A process for producing a nitrided oxide layer on a silicon semiconductor substrate includes introducing a multiplicity of wafers into an atmospheric batch furnace, carrying out an oxidation step at a first predetermined temperature, carrying out a nitriding step at a second predetermined temperature, and carrying out a reoxidation step at a third predetermined temperature. The wafers are then cooled and removed from the atmospheric batch furnace.
    Type: Application
    Filed: July 11, 2002
    Publication date: February 13, 2003
    Inventors: Ayad Abdul-Hak, Thomas Gaertner, Joerg Schulze
  • Patent number: 6368970
    Abstract: A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: April 9, 2002
    Assignee: Infineon Technologies AG
    Inventors: Ayad Abdul-Hak, Achim Gratz, Christoph Ludwig, Reinhold Rennekamp, Elard Stein Von Kamienski, Peter Wawer