Abstract: The invention relates to a method for producing an electronic system, comprising: a step of forming a plurality of interconnect paths obtained via metal deposition on the sacrificial member to form a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports; a step of depositing at least one electronic component on the lower redistribution layer; and a step of forming a plurality of three-dimensional interconnect paths obtained via metal deposition in order to connect the connectors of the electronic component to the inner connection ports of the lower redistribution layer.

Abstract: The invention relates to a method for producing an electronic system, comprising: a step of forming a plurality of interconnect paths obtained via metal deposition on the sacrificial member to form a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports; a step of depositing at least one electronic component on the lower redistribution layer; and a step of forming a plurality of three-dimensional interconnect paths obtained via metal deposition in order to connect the connectors of the electronic component to the inner connection ports of the lower redistribution layer.

Abstract: The invention relates to a method for integrating at least one interconnection for the manufacture of an integrated circuit, including a step of depositing at least one insulating body onto a substrate including a horizontal surface, said insulating body comprising a first wall extending from the horizontal surface of the substrate to a high point of said insulating body and a step of depositing a one-piece electrical structure which is made of an electrically conductive material and extends on the horizontal surface of the substrate and the first wall of the insulating body, the first wall being vertically angled by more than 10 ?m and having a rising slope extending from the horizontal surface of the substrate to the high point of said insulating body.

Abstract: The invention relates to a method for integrating at least one interconnection for the manufacture of an integrated circuit, including a step of depositing at least one insulating body onto a substrate including a horizontal surface, said insulating body comprising a first wall extending from the horizontal surface of the substrate to a high point of said insulating body and a step of depositing a one-piece electrical structure which is made of an electrically conductive material and extends on the horizontal surface of the substrate and the first wall of the insulating body, the first wall being vertically angled by more than 10 ?m and having a rising slope extending from the horizontal surface of the substrate to the high point of said insulating body.

Abstract: A high power semiconductor device for operation at powers greater than 5 watts for wireless applications comprises a semiconductor substrate including an active area of the high power semiconductor device, contact regions formed on the semiconductor substrate providing contacts to the active area of the high power semiconductor device, a dielectric layer formed over a part of the semiconductor substrate, a lead for providing an external connection to the high power semiconductor device and an impedance matching network formed on the semiconductor substrate between the active area of the high power semiconductor device and the lead. The impedance matching network includes conductor lines formed on the dielectric layer. The conductor lines are coupled to the contact regions for providing high power connections to the contact regions of the active area, and have a predetermined inductance for impedance matching.

Abstract: A method for manufacturing an integrated circuit includes the steps of: forming above an upper surface of a substrate (5) at least one dielectric layer (15) extending on an underlying surface (12), the dielectric layer (15) having an upper surface (25) and a flank (40) extending between the upper surface and the underlying surface (12); and forming an electrical structure (70) in one piece in an electrically conducting material including a structural element (75) extending on the upper surface (25) of the dielectric layer (15) and an interconnection element (80) extending from the structural element (75) along the flank (40) as far as the underlying surface. The flank has a height of more than 10 ?m, and the electrical structure is formed by depositing the electrically conducting material by simultaneously depositing the structural element on the upper surface of the dielectric layer and the interconnection element on the flank.

Abstract: A high power semiconductor device for operation at powers greater than 5 watts for wireless applications comprises a semiconductor substrate including an active area of the high power semiconductor device, contact regions formed on the semiconductor substrate providing contacts to the active area of the high power semiconductor device, a dielectric layer formed over a part of the semiconductor substrate, a lead for providing an external connection to the high power semiconductor device and an impedance matching network formed on the semiconductor substrate between the active area of the high power semiconductor device and the lead. The impedance matching network includes conductor lines formed on the dielectric layer. The conductor lines are coupled to the contact regions for providing high power connections to the contact regions of the active area, and have a predetermined inductance for impedance matching.