Patents by Inventor Ayako KAWANISHI

Ayako KAWANISHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230307387
    Abstract: A first chip includes a substrate, and first and second electrodes in a second region surrounding a first region. A second chip includes an interconnect layer, third and fourth electrodes in the second region, and first and second walls. Each of the first and third electrodes and the first wall includes a conductor surrounding the first region. The first and second electrodes are respectively in contact with the third and fourth electrodes. The first and second walls are in contact with the interconnect layer and are electrically coupled to the substrate via the first and third electrodes and the second and fourth electrodes, respectively. Each of a first ratio of an area covered by the first and second electrodes to the second region and a second ratio of an area of the third and fourth electrodes to the second region is 3% or more and 40% or less.
    Type: Application
    Filed: August 25, 2022
    Publication date: September 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Ayako KAWANISHI, Shinya ARAI
  • Publication number: 20230090711
    Abstract: According to one embodiment, a semiconductor memory device incudes: a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one; and a contact that extends in the stacked body in the stacking direction, and is connected to a structure arranged on in the stacked body or below the stacked body. The contact includes: a second conductive layer that extends in the stacked body LM in the stacking direction, and serves as a core of the contact; and a second insulating layer that covers a sidewall of the second conductive layer, and serves as a liner of the contact.
    Type: Application
    Filed: March 11, 2022
    Publication date: March 23, 2023
    Applicant: Kioxia Corporation
    Inventors: Ayako KAWANISHI, Kanako SHIGA, Takeo MORI
  • Patent number: 10692886
    Abstract: A semiconductor memory device according to an embodiment includes: a substrate; a plurality of first gate electrodes; a first semiconductor film facing the plurality of first gate electrodes; and a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film. Moreover, this semiconductor memory device includes: a plurality of second gate electrodes; a second semiconductor film facing the plurality of second gate electrodes; and a second gate insulating film provided between the plurality of second gate electrodes and the second semiconductor film. Moreover, this semiconductor memory device includes: a third gate electrode that is provided between the plurality of first gate electrodes and the plurality of second gate electrodes, and extends in a second direction; and a third gate insulating film provided between the third gate electrode and the first semiconductor film.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: June 23, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunsuke Kasashima, Jun Nishimura, Takamitsu Ochi, Hisashi Harada, Ayaha Hachisuga, Ayako Kawanishi
  • Publication number: 20200075624
    Abstract: A semiconductor memory device according to an embodiment includes: a substrate; a plurality of first gate electrodes; a first semiconductor film facing the plurality of first gate electrodes; and a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film. Moreover, this semiconductor memory device includes: a plurality of second gate electrodes; a second semiconductor film facing the plurality of second gate electrodes; and a second gate insulating film provided between the plurality of second gate electrodes and the second semiconductor film. Moreover, this semiconductor memory device includes: a third gate electrode that is provided between the plurality of first gate electrodes and the plurality of second gate electrodes, and extends in a second direction; and a third gate insulating film provided between the third gate electrode and the first semiconductor film.
    Type: Application
    Filed: March 4, 2019
    Publication date: March 5, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shunsuke KASASHIMA, Jun Nishimura, Takamitsu Ochi, Hisashi Harada, Ayaha Hachisuga, Ayako Kawanishi
  • Publication number: 20180275519
    Abstract: A pattern formation method includes forming a first pattern in a first film in a first region and forming a second pattern in the first film in a second region by using an optical lithography technology. The pattern formation method also includes forming a third pattern corresponding to the first pattern in a second film below the first film in the first region by using a self-organization lithography technology. The pattern formation method also includes transferring the third pattern to a third film below the first film and the second film in the first region and transferring the second pattern to the third film in the second region.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Ayako KAWANISHI, Takehiro Kondoh, Yusuke Kasahara
  • Patent number: 9816004
    Abstract: A pattern forming method includes forming a guide mask layer including a first feature having a first opening width, a second feature having a second opening width, a third feature having a third opening width. The first width being less than the second width and greater than the third width. A self-organizing material having a phase-separation period is disposed on the guide mask layer to at least partially fill the first, second, and third features. The self-organizing material is process to the cause phase-separation into first and second polymer portions. The first width is greater than the phase-separation period and the third width is less. A masking pattern is formed on the first layer by removing the second polymer portions and leaving the first polymer portions. The masking pattern is then transferred to the first layer.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: November 14, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Ayako Kawanishi, Yusuke Kasahara, Hiroki Yonemitsu
  • Patent number: 9685331
    Abstract: A semiconductor device manufacturing method includes forming a first film on a substrate having a first region and a second region. A second film is formed on the first film. Guide grooves are formed by removing portions of the second film and exposing the first film. A self-assembly material is coated on the exposed first film and heated to cause a phase separation into a first and a second phase section. The self-assembly material is irradiated. A mask pattern including at least a portion of the first phase section is formed by removing the second phase section. The mask pattern has a first dimension in the first region and a second dimension in the second region that is different from the first dimension. The first film is etched after the mask pattern is formed.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ayako Kawanishi, Yusuke Kasahara, Hiroki Yonemitsu
  • Publication number: 20170076952
    Abstract: A pattern forming method includes forming a guide mask layer including a first feature having a first opening width, a second feature having a second opening width, a third feature having a third opening width. The first width being less than the second width and greater than the third width. A self-organizing material having a phase-separation period is disposed on the guide mask layer to at least partially fill the first, second, and third features. The self-organizing material is process to the cause phase-separation into first and second polymer portions. The first width is greater than the phase-separation period and the third width is less. A masking pattern is formed on the first layer by removing the second polymer portions and leaving the first polymer portions. The masking pattern is then transferred to the first layer.
    Type: Application
    Filed: August 10, 2016
    Publication date: March 16, 2017
    Inventors: Ayako KAWANISHI, Yusuke KASAHARA, Hiroki YONEMITSU
  • Patent number: 9371427
    Abstract: A pattern is formed by forming a first pattern on a first film, forming a block copolymer layer including a first block chain and a second block chain on the first pattern, forming a second pattern, forming a second film on the second pattern, selectively removing the second film until the second pattern is exposed, forming a third pattern, and processing the first film using the third pattern as a mask. The second pattern is formed by microphase-separating the block copolymer layer, and removing the first block chain or the second block chain. The second film is formed by applying a material having an etch rate that is less than an etch rate of a material of the first pattern and the second pattern. The third pattern is formed by selectively removing the second pattern and the first pattern using the second film as a mask.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: June 21, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsutoshi Kobayashi, Yusuke Kasahara, Hiroki Yonemitsu, Hitoshi Kubota, Ayako Kawanishi
  • Patent number: 9279191
    Abstract: According to one embodiment, a pattern forming method includes forming a graphoepitaxy on a substrate, a process of forming a first self-assembly material layer that contains a first segment and a second segment in a depressed portion of the graphoepitaxy, a process of forming a first self-assembly pattern that has a first region containing the first segment, and a second region containing the second segment by performing a phase separation of the first self-assembly material layer, a process of forming a second self-assembly material layer containing a third segment and a fourth segment on a projected portion of the graphoepitaxy, and the first self-assembly pattern, a process of forming a second self-assembly pattern that has a third region containing the third segment, and a fourth region containing the fourth segment by performing a phase separation of the second self-assembly material layer.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: March 8, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ayako Kawanishi
  • Publication number: 20160060410
    Abstract: A pattern is formed by forming a first pattern on a first film, forming a block copolymer layer including a first block chain and a second block chain on the first pattern, forming a second pattern, forming a second film on the second pattern, selectively removing the second film until the second pattern is exposed, forming a third pattern, and processing the first film using the third pattern as a mask. The second pattern is formed by microphase-separating the block copolymer layer, and removing the first block chain or the second block chain. The second film is formed by applying a material having an etch rate that is less than an etch rate of a material of the first pattern and the second pattern. The third pattern is formed by selectively removing the second pattern and the first pattern using the second film as a mask.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 3, 2016
    Inventors: Katsutoshi KOBAYASHI, Yusuke KASAHARA, Hiroki YONEMITSU, Hitoshi KUBOTA, Ayako KAWANISHI
  • Publication number: 20150151329
    Abstract: In a pattern forming method according to the present embodiment, a first guide layer having a first pattern is formed above a base material. A second guide layer having a second pattern intersecting the first pattern is formed. A directed self-assembly material is introduced in a concave portion surrounded by the first and second guide layers. A directed self-assembly pattern having a diameter which is smaller than an opening diameter of the concave portion is formed in the concave portion by causing the directed self-assembly material to be directed self-assembled.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 4, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ayako KAWANISHI, Hirokazu Kato, Hiroki Yonemitsu, Yusuke Kasahara
  • Patent number: 9040429
    Abstract: A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Kato, Ayako Kawanishi
  • Patent number: 9040123
    Abstract: According to the embodiments, a pattern formation method includes a process of formation of a self-assembly material layer containing at least a first segment and a second segment on a substrate having a guide layer, a process of formation of a neutralization coating on the self-assembly material layer, and a process of formation of a self-assembly pattern including a first region containing the first segment and a second region containing the second segment following phase separation of the self-assembly material layer.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ayako Kawanishi, Tsukasa Azuma
  • Patent number: 9023222
    Abstract: According to one embodiment, a pattern forming method includes forming a first guide layer on a processed film, phase-separating a first self-assembly material with the use of the first guide layer to form a first self-assembly pattern including a first polymer portion and a second polymer portion, selectively removing the first polymer portion, forming a second guide layer with the use of the second polymer portion, and phase-separating a second self-assembly material with the use of the second guide layer to form a second self-assembly pattern including a third polymer portion and a fourth polymer portion.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ayako Kawanishi, Shinichi Ito, Hirokazu Kato, Shimon Maeda, Hideki Kanai
  • Patent number: 8999853
    Abstract: A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Kato, Ayako Kawanishi
  • Patent number: 8980755
    Abstract: According to the embodiments, a method for pattern formation includes: creating a first self-assembly material layer which contains a first segment and a second segment, on a substrate on which a guide layer is installed; creating a first self-assembled pattern in which the first self-assembly material layer is phase-separated, the pattern including a first area containing the first segment and a second area containing the second segment; creating a second self-assembly material layer which includes a third segment and a fourth segment, in the first self-assembled pattern; creating a second self-assembled pattern in which the second self-assembly material layer is phase-separated, and which includes a third area containing the third segment and a fourth area containing the fourth segment.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ayako Kawanishi, Tsukasa Azuma
  • Publication number: 20140295669
    Abstract: According to one embodiment, a pattern forming method includes forming a first guide layer on a processed film, phase-separating a first self-assembly material with the use of the first guide layer to form a first self-assembly pattern including a first polymer portion and a second polymer portion, selectively removing the first polymer portion, forming a second guide layer with the use of the second polymer portion, and phase-separating a second self-assembly material with the use of the second guide layer to form a second self-assembly pattern including a third polymer portion and a fourth polymer portion.
    Type: Application
    Filed: September 5, 2013
    Publication date: October 2, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ayako KAWANISHI, Shinichi Ito, Hirokazu Kato, Shimon Maeda, Hideki Kanai
  • Publication number: 20140248439
    Abstract: According to one embodiment, a pattern formation method includes coating a polymer material on a film to be processed, the polymer material having a first segment and a second segment, the second segment containing a functional group that causes a cross-linking reaction, performing microphase separation of the polymer material to form a self-assembly pattern having a first polymer portion that contains the first segment and a second polymer portion that contains the second segment, performing irradiation with energy rays toward the self-assembly pattern in a cooling state; and selectively removing the first polymer portion.
    Type: Application
    Filed: August 1, 2013
    Publication date: September 4, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu SATO, Yuriko SEINO, Masahiro KANNO, Hirokazu KATO, Katsutoshi KOBAYASHI, Hiroki YONEMITSU, Ayako KAWANISHI
  • Publication number: 20140087566
    Abstract: A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film.
    Type: Application
    Filed: March 4, 2013
    Publication date: March 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirokazu KATO, Ayako KAWANISHI