Abstract: A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined based on the number of times. The non-linearity values are stored in a memory.

Abstract: A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.

Abstract: A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined based on the number of times. The non-linearity values are stored in a memory.

Abstract: A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.

Abstract: A re-timer device includes transceiver circuitry. The transceiver circuitry includes clock generation circuitry and first receiver circuitry. The clock generation circuitry generates a first clock signal. The first receiver circuitry receives the first clock signal and a first input signal. The first receiver circuitry generates a first frequency offset value based on the first input signal and the first clock signal. The first input signal has a first frequency and the first clock signal has a second frequency different than the first frequency. The first receiver circuitry outputs the first frequency offset value.