Patents by Inventor Ayan Datta
Ayan Datta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10678981Abstract: A computer-implemented method includes receiving a text description of a logic circuit design, reading a plurality of circuit priority indicator values, synthesizing a logic circuit design based, at least in part, on those circuit priority indicator values, and fabricating logic circuits using the synthesized logic circuit design. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: October 3, 2018Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock
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Publication number: 20190034563Abstract: A computer-implemented method includes receiving a text description of a logic circuit design, reading a plurality of circuit priority indicator values, synthesizing a logic circuit design based, at least in part, on those circuit priority indicator values, and fabricating logic circuits using the synthesized logic circuit design. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: October 3, 2018Publication date: January 31, 2019Inventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock
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Patent number: 10133840Abstract: A computer-implemented method includes receiving, with one or more processors, a text-based description of a logic circuit comprising a plurality of logic sub-circuits, determining within the text-based description, with one or more processors, a set of circuit priority indicators for a corresponding set of the logic sub-circuits, and synthesizing, with one or more processors, the logic circuit according to the set of circuit priority indicators to provide a synthesized circuit description. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: December 4, 2015Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock
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Patent number: 10062709Abstract: A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.Type: GrantFiled: September 26, 2016Date of Patent: August 28, 2018Assignee: International Business Machines CorporationInventors: Ayan Datta, Ankur Shukla, James D. Warnock
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Publication number: 20180181686Abstract: A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design.Type: ApplicationFiled: March 14, 2018Publication date: June 28, 2018Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
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Publication number: 20180181687Abstract: A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design.Type: ApplicationFiled: March 14, 2018Publication date: June 28, 2018Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
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Patent number: 10002881Abstract: A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.Type: GrantFiled: January 18, 2017Date of Patent: June 19, 2018Assignee: International Business Machines CorporationInventors: Ayan Datta, Ankur Shukla, James D. Warnock
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Patent number: 9985616Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.Type: GrantFiled: January 3, 2017Date of Patent: May 29, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock
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Patent number: 9965576Abstract: A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design.Type: GrantFiled: July 21, 2017Date of Patent: May 8, 2018Assignee: International Business Machines CorporationInventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
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Patent number: 9953121Abstract: A computer-implemented method includes identifying an in initial register-transfer-level description for an integrated circuit design and adding one or more spare latches to the initial register-transfer-level description to yield a modified register-transfer-level description for the integrated circuit design. The computer-implemented method further includes performing placement and routing for the modified register-transfer-level description to yield a gate-level description for the integrated circuit design. The one or more spare latches exist in said gate-level description. The computer-implemented method further includes converting at least one of the one or more spare latches in the gate-level description into a reconfigurable latch filler cell to yield a modified gate-level description for the integrated circuit design and finalizing the integrated circuit design. A corresponding computer program product and computer system are also disclosed.Type: GrantFiled: May 3, 2016Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
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Publication number: 20180090514Abstract: A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.Type: ApplicationFiled: January 18, 2017Publication date: March 29, 2018Inventors: Ayan Datta, Ankur Shukla, James D. Warnock
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Publication number: 20180090513Abstract: A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.Type: ApplicationFiled: September 26, 2016Publication date: March 29, 2018Inventors: Ayan Datta, Ankur Shukla, James D. Warnock
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Publication number: 20170323032Abstract: A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design.Type: ApplicationFiled: July 21, 2017Publication date: November 9, 2017Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
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Publication number: 20170323030Abstract: A computer-implemented method includes identifying an in initial register-transfer-level description for an integrated circuit design and adding one or more spare latches to the initial register-transfer-level description to yield a modified register-transfer-level description for the integrated circuit design. The computer-implemented method further includes performing placement and routing for the modified register-transfer-level description to yield a gate-level description for the integrated circuit design. The one or more spare latches exist in said gate-level description. The computer-implemented method further includes converting at least one of the one or more spare latches in the gate-level description into a reconfigurable latch filler cell to yield a modified gate-level description for the integrated circuit design and finalizing the integrated circuit design. A corresponding computer program product and computer system are also disclosed.Type: ApplicationFiled: May 3, 2016Publication date: November 9, 2017Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
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Publication number: 20170161406Abstract: A computer-implemented method includes receiving, with one or more processors, a text-based description of a logic circuit comprising a plurality of logic sub-circuits, determining within the text-based description, with one or more processors, a set of circuit priority indicators for a corresponding set of the logic sub-circuits, and synthesizing, with one or more processors, the logic circuit according to the set of circuit priority indicators to provide a synthesized circuit description. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: December 4, 2015Publication date: June 8, 2017Inventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock
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Publication number: 20170126218Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.Type: ApplicationFiled: January 3, 2017Publication date: May 4, 2017Inventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock
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Patent number: 9614507Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.Type: GrantFiled: September 2, 2015Date of Patent: April 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock
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Publication number: 20170012616Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.Type: ApplicationFiled: September 2, 2015Publication date: January 12, 2017Inventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock
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Publication number: 20170012615Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.Type: ApplicationFiled: July 8, 2015Publication date: January 12, 2017Inventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock
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Patent number: 9543935Abstract: Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.Type: GrantFiled: July 8, 2015Date of Patent: January 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan, James D. Warnock