Patents by Inventor Ayan PAUL
Ayan PAUL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12367927Abstract: A memory is provided with a pseudo-differential sense amplifier for single-endedly sensing a first read bit line from a first bank of bitcells. The sense amplifier compares a voltage of the first read bit line to a voltage of a pre-charged second read bit line from a second bank of bitcells to make a bit decision for a read operation through the first read bit line to the first bank of bitcells.Type: GrantFiled: January 31, 2023Date of Patent: July 22, 2025Assignee: QUALCOMM INCORPORATEDInventors: Chulmin Jung, David Li, Po-Hung Chen, Ayan Paul, Derek Yang, Chun-Yen Lin
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Publication number: 20240257868Abstract: A memory is provided with a pseudo-differential sense amplifier for single-endedly sensing a first read bit line from a first bank of bitcells. The sense amplifier compares a voltage of the first read bit line to a voltage of a pre-charged second read bit line from a second bank of bitcells to make a bit decision for a read operation through the first read bit line to the first bank of bitcells.Type: ApplicationFiled: January 31, 2023Publication date: August 1, 2024Inventors: Chulmin JUNG, David LI, Po-Hung CHEN, Ayan PAUL, Derek YANG, Chun-Yen LIN
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Patent number: 11908537Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.Type: GrantFiled: February 1, 2023Date of Patent: February 20, 2024Assignee: QUALCOMM IncorporatedInventors: David Li, Rahul Biradar, Biju Manakkam Veetil, Po-Hung Chen, Ayan Paul, Sung Son, Shivendra Kushwaha, Ravindra Reddy Chekkera, Derek Yang
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Publication number: 20230178118Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.Type: ApplicationFiled: February 1, 2023Publication date: June 8, 2023Inventors: David LI, Rahul BIRADAR, Biju MANAKKAM VEETIL, Po-Hung CHEN, Ayan PAUL, Sung SON, Shivendra KUSHWAHA, Ravindra Reddy CHEKKERA, Derek YANG
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Patent number: 11600307Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.Type: GrantFiled: December 29, 2020Date of Patent: March 7, 2023Assignee: QUALCOMM INCORPORATEDInventors: David Li, Rahul Biradar, Biju Manakkam Veetil, Po-Hung Chen, Ayan Paul, Sung Son, Shivendra Kushwaha, Ravindra Reddy Chekkera, Derek Yang
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Patent number: 11450359Abstract: Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.Type: GrantFiled: July 2, 2021Date of Patent: September 20, 2022Assignee: QUALCOMM INCORPORATEDInventors: Xiao Chen, Po-Hung Chen, Chen-ju Hsieh, David Li, Chulmin Jung, Ayan Paul
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Publication number: 20220208232Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventors: David LI, Rahul BIRADAR, Biju MANAKKAM VEETIL, Po-Hung CHEN, Ayan PAUL, Sung SON, Shivendra KUSHWAHA, Ravindra Reddy CHEKKERA, Derek YANG
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Publication number: 20190087086Abstract: A method for providing context based multimodal predictions in an electronic device is provided. The method includes detecting an input on a touch screen keyboard displayed on a screen of the electronic device. Further, the method includes generating one or more context based multimodal predictions based on the detected input from a language model. Furthermore, the method includes displaying the one or more context based multimodal predictions in the electronic device. An electronic device includes a processor configured to detect an input through a touch screen keyboard displayed on a screen of the electronic device, generate one or more context based multimodal predictions in accordance with the detected input from a language model, and cause the screen to display the one or more context based multimodal predictions in the electronic device.Type: ApplicationFiled: August 29, 2018Publication date: March 21, 2019Inventors: Barath Raj KANDUR RAJA, Arko SABUI, Ayan PAUL, Ketki Aniruddha GUPTE, Himanshu ARORA, Vibhav AGARWAL, Yellappa DAMAM