Patents by Inventor Ayao Yokoyama

Ayao Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7043704
    Abstract: The present invention provides a method for verifying a design of a circuit board that has a wiring layer connecting components to be mounted, a power layer, and an insulating layer formed between the wiring layer and the power layer. According to this method, detection of chippings in the power layer is performed. The chipping is, for example, a gap, a slot, or a slit, and corresponds to one wiring layer and interrupts a region in which the wiring layer and the power layer are opposed to each other. When chippings are detected, a common-mode voltage expected to be caused owing to each of the chippings is computed. Subsequently, the position of the chipping and the value of the common-mode voltage caused owing to the chipping are outputted. Thus, the priorities of the chippings, to which countermeasure for suppressing radiation of electromagnetic waves should be applied, can easily be decided.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: May 9, 2006
    Assignee: Sony Corporation
    Inventors: Kenji Araki, Ayao Yokoyama
  • Patent number: 6799306
    Abstract: Layout of a high-speed signal wiring on a power supply plane is checked and specified at an optimum position capable of minimizing a spurious electromagnetic radiation so as not to affect other wiring layers. When a high speed signal line which is an object to be checked exists on a power supply plane, a perpendicular distance between the high speed signal line and the plane which is nearest to the signal line is determined, and compared with a minimum required distance computed therefor in advance on the basis of its circuit specification of the high speed signal line. If the perpendicular distance determined does not exceed the minimum required distance computed, an appropriate message corresponding to the name of the high speed signal line is displayed.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: September 28, 2004
    Assignee: Sony Corporation
    Inventors: Kenji Araki, Ayao Yokoyama
  • Patent number: 6704919
    Abstract: The check system comprises the steps of: computing the optimum position and the optimum capacitance value of the bulk capacitor on a wiring printed circuit board mounting an IC which is an object of checkup, using simple mathematical expressions; determining if an actual capacitance value and an actual position of the bulk capacitor tentatively designed are nearly equal to the optimum value and optimum position computed; determining if the tentatively designed capacitance value of the bulk capacitor exceeds a value of a total sum of capacitance values of decoupling capacitors multiplied by a predetermined constant; and if the optimum conditions are not satisfied, displaying appropriate instructions to modify the tentative design value and position of the bulk capacitor to coincide with the optimum value and position.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: March 9, 2004
    Assignee: Sony Corporation
    Inventors: Kenji Araki, Ayao Yokoyama
  • Patent number: 6681375
    Abstract: A check system for a wiring structure of a printed circuit board for easily calculating an electric energy of a high-speed signal wiring on the printed circuit board and warning when the energy owned by the signal wiring is larger than a designated threshold value. The electric energy radiated from the high-speed signal wiring intended for checking is calculated by using a simple mathematical expression, and a display to identify the signal wiring is outputted when the electric energy owned by the signal wiring is larger than a certain designated threshold value, and also an instructing message to relocate in an internal layer of the circuit board is outputted against the signal wiring.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: January 20, 2004
    Inventors: Kenji Araki, Ayao Yokoyama
  • Publication number: 20040003358
    Abstract: The present invention provides a method for verifying a design of a circuit board that has a wiring layer connecting components to be mounted, a power layer, and an insulating layer formed between the wiring layer and the power layer. According to this method, detection of chippings in the power layer is performed. The chipping is, for example, a gap, a slot, or a slit, and corresponds to one wiring layer and interrupts a region in which the wiring layer and the power layer are opposed to each other. When chippings are detected, a common-mode voltage expected to be caused owing to each of the chippings is computed. Subsequently, the position of the chipping and the value of the common-mode voltage caused owing to the chipping are outputted. Thus, the priorities of the chippings, to which countermeasure for suppressing radiation of electromagnetic waves should be applied, can easily be decided.
    Type: Application
    Filed: June 11, 2003
    Publication date: January 1, 2004
    Inventors: Kenji Araki, Ayao Yokoyama
  • Publication number: 20020017907
    Abstract: The check system comprises the steps of: computing the optimum position and the optimum capacitance value of the bulk capacitor on a wiring printed circuit board mounting an IC which is an object of checkup, using simple mathematical expressions; determining if an actual capacitance value and an actual position of the bulk capacitor tentatively designed are nearly equal to the optimum value and optimum position computed; determining if the tentatively designed capacitance value of the bulk capacitor exceeds a value of a total sum of capacitance values of decoupling capacitors multiplied by a predetermined constant; and if the optimum conditions are not satisfied, displaying appropriate instructions to modify the tentative design value and position of the bulk capacitor to coincide with the optimum value and position.
    Type: Application
    Filed: June 26, 2001
    Publication date: February 14, 2002
    Applicant: Sony Corporation
    Inventors: Kenji Araki, Ayao Yokoyama
  • Publication number: 20020019970
    Abstract: Layout of a high-speed signal wiring on a power supply plane is checked and specified at an optimum position capable of minimizing a spurious electromagnetic radiation so as not to affect other wiring layers. When a high speed signal line which is an object to be checked exists on a power supply plane, a perpendicular distance between the high speed signal line and the plane which is nearest to the signal line is determined, and compared with a minimum required distance computed therefor in advance on the basis of its circuit specification of the high speed signal line. If the perpendicular distance determined does not exceed the minimum required distance computed, an appropriate message corresponding to the name of the high speed signal line is displayed.
    Type: Application
    Filed: June 1, 2001
    Publication date: February 14, 2002
    Inventors: Kenji Araki, Ayao Yokoyama
  • Publication number: 20020007260
    Abstract: A check system for a wiring structure of a printed circuit board for easily calculating an electric energy of a high-speed signal wiring on the printed circuit board and warning when the energy owned by the signal wiring is larger than a designated threshold value. The electric energy radiated from the high-speed signal wiring intended for checking is calculated by using a simple mathematical expression, and a display to identify the signal wiring is outputted when the electric energy owned by the signal wiring is larger than a certain designated threshold value, and also an instructing message to relocate in an internal layer of the circuit board is outputted against the signal wiring.
    Type: Application
    Filed: July 13, 2001
    Publication date: January 17, 2002
    Applicant: Sony Corporation
    Inventors: Kenji Araki, Ayao Yokoyama