Patents by Inventor Ayesha Akhter

Ayesha Akhter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11922130
    Abstract: In an approach for optimization of integer arithmetic expressions implemented as a Boolean logic circuit, a processor converts arithmetic operators in an arithmetic expression into adders. A processor identifies a topological order of the adders. A processor merges the adders based on the topological order into a multi-operand adder. A processor converts the multi-operand adder to a compressor tree and a two-operand adder. A processor performs the arithmetic expression based on the converted multi-operand adder.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: March 5, 2024
    Assignee: International Business Machines Corporation
    Inventors: Mihir Choudhury, Ayesha Akhter, Alexander Ivrii, Robert Lowell Kanzelman
  • Publication number: 20230394212
    Abstract: An example system includes a processor to receive a high-level design representation of a system architecture. The processor can synthesize a logic design and generate an associated synthesis history based on the high-level hardware design representation. The processor can then execute an equivalence check between the high-level design and the synthesized logic design based on the generated synthesis history.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Alexander IVRII, Jason Raymond BAUMGARTNER, Robert Lowell KANZELMAN, Mark Allen WILLIAMS, Mihir CHOUDHURY, Ayesha AKHTER
  • Publication number: 20230185528
    Abstract: In an approach for optimization of integer arithmetic expressions implemented as a Boolean logic circuit, a processor converts arithmetic operators in an arithmetic expression into adders. A processor identifies a topological order of the adders. A processor merges the adders based on the topological order into a multi-operand adder. A processor converts the multi-operand adder to a compressor tree and a two-operand adder. A processor performs the arithmetic expression based on the converted multi-operand adder.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Inventors: MIHIR CHOUDHURY, Ayesha Akhter, ALEXANDER IVRII, Robert Lowell Kanzelman
  • Patent number: 8463571
    Abstract: A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: June 11, 2013
    Assignee: International Business Machines Corporation
    Inventors: Soroush Abbaspour, Ayesha Akhter, Peter Feldmann, Joachim Keinert
  • Publication number: 20120123725
    Abstract: A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 17, 2012
    Applicant: International Business Machines Corporation
    Inventors: Soroush Abbaspour, Ayesha Akhter, Peter Feldmann, Joachim Keinert
  • Patent number: 7685549
    Abstract: A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Debjit Sinha, Soroush Abbaspour, Ayesha Akhter, Gregory M. Schaeffer, David J. Widiger
  • Publication number: 20090077515
    Abstract: A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Debjit Sinha, Soroush Abbaspour, Ayesha Akhter, Gregory M. Schaeffer, David J. Widiger