Patents by Inventor Ayman A. Fayed
Ayman A. Fayed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8390496Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network. computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.Type: GrantFiled: February 23, 2010Date of Patent: March 5, 2013Assignee: Texas Instruments IncorporatedInventors: Ayman A. Fayed, Russell Byrd, Baher Haroun
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Patent number: 8330159Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.Type: GrantFiled: November 1, 2007Date of Patent: December 11, 2012Assignee: Texas Instruments IncorporatedInventors: Jeffrey Lee Large, Henry Litzmann Edwards, Ayman A. Fayed, Patrick Cruise, Kah Mun Low, Neeraj Nayak, Oguz Altun, Chris Barr
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Patent number: 8120425Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.Type: GrantFiled: February 23, 2010Date of Patent: February 21, 2012Assignee: Texas Instruments IncorporatedInventors: Ayman A. Fayed, Russell Byrd, Baher Haroun
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Patent number: 7994819Abstract: One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first control node and the second control node based on an input signal to set a first initial voltage at the first control node and a second initial voltage at the second control node, the input signal having logic-high and logic-low voltage magnitudes that occupy a low voltage domain. The circuit also includes a logic driver that is coupled to the second control node and is referenced in a high voltage domain. The logic driver can be configured to provide an output signal having logic-high and logic-low voltage magnitudes that occupy the high voltage domain based on the second initial voltage.Type: GrantFiled: December 30, 2008Date of Patent: August 9, 2011Assignee: Texas Instruments IncorporatedInventors: Mohammad A. Al-Shyoukh, Ayman A. Fayed
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Patent number: 7907429Abstract: A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a digitally controlled transfer capacitor. A pair of non-overlapping, fixed frequency clock signals is provided to a switched capacitor circuit including the switched capacitor matrix and a load capacitor coupled to the output terminal. A DC input voltage supply is provided. A hysteretic feedback loop is used to control the voltage at the output as a stepped-down voltage from the input by digitally modulating the transfer capacitor using switches in the switch matrix to couple more, or fewer, transfer capacitors to the output terminal during a clock cycle. A coarse and a fine adjustment circuit are provided to improve the regulation during rapid changes in load power. A method of operating the regulator is disclosed.Type: GrantFiled: December 31, 2007Date of Patent: March 15, 2011Assignee: Texas Instruments IncorporatedInventors: Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun
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Patent number: 7796066Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.Type: GrantFiled: February 23, 2010Date of Patent: September 14, 2010Assignee: Texas Instruments IncorporatedInventors: Ayman A. Fayed, Russell Byrd, Baher Haroun
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Publication number: 20100156497Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.Type: ApplicationFiled: February 23, 2010Publication date: June 24, 2010Inventors: Ayman A. Fayed, Russell Byrd, Baher Haroun
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Publication number: 20100149013Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.Type: ApplicationFiled: February 23, 2010Publication date: June 17, 2010Inventors: Ayman A. Fayed, Russell Byrd, Baher Haroun
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Publication number: 20100117682Abstract: One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first control node and the second control node based on an input signal to set a first initial voltage at the first control node and a second initial voltage at the second control node, the input signal having logic-high and logic-low voltage magnitudes that occupy a low voltage domain. The circuit also includes a logic driver that is coupled to the second control node and is referenced in a high voltage domain. The logic driver can be configured to provide an output signal having logic-high and logic-low voltage magnitudes that occupy the high voltage domain based on the second initial voltage.Type: ApplicationFiled: December 30, 2008Publication date: May 13, 2010Inventors: Mohammad A. Al-Shyoukh, Ayman A. Fayed
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Patent number: 7679443Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.Type: GrantFiled: March 29, 2007Date of Patent: March 16, 2010Assignee: Texas Instruments IncorporatedInventors: Ayman A. Fayed, Russell Byrd, Baher Haroun
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Patent number: 7675345Abstract: Low-leakage level-shifters with reduced leakage are disclosed. In one example, a level-shifter circuit to reduce leakage when there is an invalid supply voltage is described, including a level-shifter configured to shift a voltage of an digital input signal based on a first supply voltage to a digital output signal based on a second supply voltage, comprising a first transistor and a second transistor configured to set the digital output signal based on the digital input signal, a supply detector configured to generate a detection signal based on the first supply voltage, a disabler configured to, based on the detection signal, set the digital output signal of the level-shifter to a predetermined state, and a leakage reducer configured to, based on the detection signal, electrically disconnect the first and second transistors from the level-shifter.Type: GrantFiled: July 21, 2008Date of Patent: March 9, 2010Assignee: Texas Instruments IncorporatedInventor: Ayman A. Fayed
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Patent number: 7548824Abstract: A system and method for an automated analysis system for semiconductor manufacturing fabrication is disclosed. The system includes one or more site databases that each store data generated by an associated one or more semiconductor fabrication plants, a configuration database, and a server communicatively coupled to the one or more site databases and the configuration database, the server to analyze the data from the one or more site databases upon a request by a client, the data to be analyzed based on configuration settings in the configuration database that provide uniform configuration synchronization for applying algorithms to the data.Type: GrantFiled: June 27, 2006Date of Patent: June 16, 2009Assignee: Intel CorporationInventors: Sutirtha Bhattacharya, Brenda Buttrick, David Eggleston, Ayman Fayed, Raj Mohan, Girish Nirgude, Sanjay Patel, Ashit Sawhney, Raghu Yeluri
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Publication number: 20090114912Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Applicant: Texas Instruments IncorporatedInventors: Jeffrey Lee Large, Henry Litzmann Edwards, Ayman A. Fayed, Patrick Cruise, Kah Mun Low, Neeraj Nayak, Oguz Altun, Chris Barr
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Publication number: 20090072800Abstract: A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a digitally controlled transfer capacitor. A pair of non-overlapping, fixed frequency clock signals is provided to a switched capacitor circuit including the switched capacitor matrix and a load capacitor coupled to the output terminal. A DC input voltage supply is provided. A hysteretic feedback loop is used to control the voltage at the output as a stepped-down voltage from the input by digitally modulating the transfer capacitor using switches in the switch matrix to couple more, or fewer, transfer capacitors to the output terminal during a clock cycle. A coarse and a fine adjustment circuit are provided to improve the regulation during rapid changes in load power. A method of operating the regulator is disclosed.Type: ApplicationFiled: December 31, 2007Publication date: March 19, 2009Inventors: Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun
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Publication number: 20090027102Abstract: Low-leakage level-shifters with reduced leakage are disclosed. In one example, a level-shifter circuit to reduce leakage when there is an invalid supply voltage is described, including a level-shifter configured to shift a voltage of an digital input signal based on a first supply voltage to a digital output signal based on a second supply voltage, comprising a first transistor and a second transistor configured to set the digital output signal based on the digital input signal, a supply detector configured to generate a detection signal based on the first supply voltage, a disabler configured to, based on the detection signal, set the digital output signal of the level-shifter to a predetermined state, and a leakage reducer configured to, based on the detection signal, electrically disconnect the first and second transistors from the level-shifter.Type: ApplicationFiled: July 21, 2008Publication date: January 29, 2009Inventor: Ayman A. Fayed
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Publication number: 20080238746Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Inventors: Ayman A. Fayed, Russell Byrd, Baher Haroun
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Publication number: 20070299634Abstract: In one embodiment, a system and method for an automated analysis system for semiconductor manufacturing fabrication is disclosed. In one embodiment, the system comprises one or more site databases that each store data generated by an associated one or more semiconductor fabrication plants, a configuration database, and a server communicatively coupled to the one or more site databases and the configuration database, the server to analyze the data from the one or more site databases upon a request by a client, the data to be analyzed based on configuration settings in the configuration database that provide uniform configuration synchronization for applying algorithms to the data. Other embodiments are also described.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventors: Sutirtha Bhattacharya, Brenda Buttrick, David Eggleston, Ayman Fayed, Raj Mohan, Girish Nirgude, Sanjay Patel, Ashit Sawhney, Raghu Yeluri
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Patent number: 6724258Abstract: A voltage controlled transconductor (VCT) for receiving a differential input signal comprising a first voltage signal and a second voltage signal, and for providing a differential output signal comprising a first output current signal and a second output current signal. The VCT includes a first side transconductor circuit having two parts of the same construction, the first part being capable of conducting a first current signal and the second part being capable of conducting a second current signal, the first current signal and the second current signal being controlled by the first voltage signal. The VCT also includes a second side transconductor circuit having two parts of the same construction, the first part being capable of conducting a third current signal and the second part being capable of conducting a fourth current signal, the third current signal and the fourth current signal being controlled by the second voltage signal.Type: GrantFiled: December 4, 2002Date of Patent: April 20, 2004Assignee: Texas Instruments IncorporatedInventor: Ayman A. Fayed
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Patent number: 6400219Abstract: A high-speed differential offset comparator circuit, providing a comparator function at a predetermined offset voltage. The differential offset comparator circuit includes a substantially zero offset comparator circuit having a first and a second differential input. The differential offset comparator circuit also includes a first pre-amplifier circuit and a second pre-amplifier circuit having an output coupled to the first and the second differential input, respectively, of the substantially zero offset comparator circuit. The pre-amplifier circuits are capable of providing a controllable offset to the differential offset comparator circuit. Each pre-amplifier circuit includes a first MOS transistor and a second MOS transistor connected in series to form a first composite transistor having an effective source, gate and drain. The first MOS transistor receives an input of the differential offset comparator circuit at a gate thereof.Type: GrantFiled: August 16, 2000Date of Patent: June 4, 2002Assignee: Texas Instruments IncorporatedInventor: Ayman A. Fayed