Patents by Inventor Ayman G. Abdo

Ayman G. Abdo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Microprocessor design support for computer system and platform validation
    Patent number: 7487398
    Abstract: Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: February 3, 2009
    Assignee: Intel Corporation
    Inventors: Ayman G. Abdo, Cameron McNairy, Piyush Desai, Quinn W. Merrell
  • Microprocessor design support for computer system and platform validation
    Patent number: 7032134
    Abstract: A validation FUB is a hardware system within the agent that can place a computer system in a stress condition. A validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions. The validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: April 18, 2006
    Assignee: Intel Corporation
    Inventors: Ayman G. Abdo, Cameron McNairy, Piyush Desai, Quinn W. Merrell
  • Automatic testing for multi-core architecture
    Patent number: 6907548
    Abstract: A test circuit disposed between a common bus and the cores of a multi-core computer permits post-silicon validation in the form of controlled stress testing of the system. The test circuit may block data requests from one or more selected cores and issue test data requests into the system instead, resulting in a more controllable test environment. In one embodiment, the test circuit is programmed and monitored from an external device through an integrated test port.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: June 14, 2005
    Assignee: Intel Corporation
    Inventor: Ayman G. Abdo
  • Automatic testing for multi-core architecture
    Publication number: 20030126515
    Abstract: A test circuit disposed between a common bus and the cores of a multi-core computer permits post-silicon validation in the form of controlled stress testing of the system. The test circuit may block data requests from one or more selected cores and issue test data requests into the system instead, resulting in a more controllable test environment. In one embodiment, the test circuit is programmed and monitored from an external device through an integrated test port.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventor: Ayman G. Abdo
  • Microprocessor design support for computer system and platform validation
    Publication number: 20020144183
    Abstract: A validation FUB is a hardware system within the agent that can place a computer system in a stress condition. A validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions. The validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.
    Type: Application
    Filed: March 28, 2001
    Publication date: October 3, 2002
    Inventors: Ayman G. Abdo, Cameron McNairy, Piyush Desai, Quinn W. Merrelle