Abstract: Selecting an optimized, geometrically diverse subset of clips for a design layout for a semiconductor wafer is described. A complete representation of the design layout is received. A set of representative clips of the design layout is determined such that individual representative clips comprise different combinations of one or more unique patterns of the design layout. A subset of the representative clips is selected based on the one or more unique patterns. The subset of the representative clips is configured to include: (1) each geometrically unique pattern in a minimum number of representative clips; or (2) as many geometrically unique patterns of the design layout as possible in a maximum number of representative clips. The subset of representative clips is provided as training data for training an optical proximity correction or source mask optimization semiconductor process machine learning model, for example.

Abstract: A method for generating a mask pattern for a lithographic process. The method involves generating a smoothed representation of a segmented mask pattern by applying a first smoothing function and adjusting the segmented mask pattern by with a set of changes to one or more of the plurality of segmented features. Further, a patterning process simulation is performed in an iterative manner by using the smoothed mask pattern of an adjusted segmented mask pattern until a termination condition is satisfied. In each iteration, upon adjusting the segmented mask pattern, a smoothed mask pattern is generated and used by process models to simulate the patterning process. Once the termination condition is satisfied, a resultant segmented mask pattern is obtained. Then, a final mask pattern is generated by applying a second smoothing function to a resultant segmented mask pattern.

Abstract: Identification of error clusters in an image predicted by a simulation model (e.g., a machine learning model), and training or adjusting the simulation model by feeding the error cluster information back to the simulation model to improve the prediction in regions of the image having the error clusters. Further, embodiments are disclosed for scoring the predicted images, or the simulation models generating those predicted images, based on a severity of errors in the error clusters. The score may be used in evaluating the simulation models to select a specific simulation model for generating a predicted image that may be used in manufacturing a mask to print a desired pattern on a substrate.

Abstract: A method and apparatus for selecting patterns for training or calibrating models related to semiconductor manufacturing. The method includes obtaining a first set of patterns; representing each pattern of the first set of patterns in a representation domain, the representation domain corresponding to electromagnetic functions; and selecting a second set of patterns from the first set of patterns based on the representation domain.

Abstract: A method for generating a retargeted pattern for a target pattern to be printed on a substrate. The method includes obtaining (i) the target pattern comprising at least one feature, the at least one feature having geometry including a first dimension and a second dimension, and (ii) a plurality of biasing rules defined as a function of the first dimension, the second dimension, and a property associated with features of the target pattern within a measurement region; determining values of the property at a plurality of locations on the at least one feature of the target pattern, each location surrounded by the measurement region; selecting, from the plurality of biasing rules based on the values of the property, a sub-set of biases; and generating the retargeted pattern by applying the selected sub-set of biases to the at least one feature of the target pattern.

Abstract: A method for verifying a feature of a mask design. The method includes determining localized shapes of the feature, and determining whether there is a breach by the feature of verification criteria based on the localized shapes. The verification criteria specifies correspondence between a threshold of a pattern characteristic and a localized shape. For example, the feature of the mask design may be a freeform curvilinear mask feature. The localized shapes may include local curvatures of individual locations on segments of the feature. In some embodiments, the threshold of the pattern characteristic is a spacing threshold, and the verification criteria specifies the spacing threshold as a function of the local curvatures. The method may facilitate enhanced mask rules checks (MRC), including better definition and verification of MRC criteria for freeform curvilinear masks, and/or have other advantages.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to curvilinear mask models and methods of manufacture. The method includes: calibrating, by a computing device, machine learning models for silicon photonics applications; retargeting, by the computing device, designs in a layout for the silicon photonics applications by applying the machine learning models to the designs; and repairing, by the computing device, unmatching shapes in the retargeted designs to generate final curvilinear mask shapes for the silicon photonics application.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to curvilinear mask models and methods of manufacture. The method includes: calibrating, by a computing device, machine learning models for silicon photonics applications; retargeting, by the computing device, designs in a layout for the silicon photonics applications by applying the machine learning models to the designs; and repairing, by the computing device, unmatching shapes in the retargeted designs to generate final curvilinear mask shapes for the silicon photonics application.

Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

Abstract: A method of providing self-aligned via (SAV) awareness in optical proximity correction (OPC) includes identifying non-SAV edges, identifying any lower metal structure that is within a critical distance from the non-SAV edges, and defining replacement non-SAV edges proximate to the lower metal structure using a distance constraint that is evaluated as part of the OPC objective function to redefine the mask solution and relocate at least one non-SAV edge away from the lower metal structure.

Abstract: A method of providing self-aligned via (SAV) awareness in optical proximity correction (OPC) includes identifying non-SAV edges, identifying any lower metal structure that is within a critical distance from the non-SAV edges, and defining replacement non-SAV edges proximate to the lower metal structure using a distance constraint that is evaluated as part of the OPC objective function to redefine the mask solution and relocate at least one non-SAV edge away from the lower metal structure.

Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

Abstract: A method for modifying an integrated circuit layout design includes providing an initial multiple-patterned circuit layout design comprising a first pattern exposure and a second pattern exposure; modifying the initial multiple-patterned circuit layout design by providing a subresolution assist feature to the first pattern exposure; determining whether the presence of any overlapping areas between the subresolution assist feature of the first pattern exposure and the second pattern exposure; and further modifying the initial multiple-patterned circuit layout design by: maintaining the size of any portion of the subresolution assist feature in the overlapping areas; and shrinking the size of any portion of the subresolution assist feature that is not in the overlapping areas.

Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

Abstract: Embodiments of the present invention provide a system and method for SAV (self-aligned via) retargeting. The SAV (Self Aligned Vias) process aids in the alignment of the vias with the metal above (Mx+1) during the dual damascene process. The retargeting enables an increase the area of the via during photolithography without affecting the final critical dimension. SAV retargeting is the via retargeting during the mask tape-out to reshape the via and protect it against possible via-to-Mx+1 overlay error. With embodiments of the present invention, the via edge movement is linked to the actual driver behind the SAV retargeting, which is maintaining a minimum area coverage with the metal above at extreme overlay error conditions. Accordingly, for a via edge to get SAV retargeted, a calculation is first made to determine how much its opposite via edge is subject to be cut during SAV due to overlay error.

Abstract: A method for modifying an integrated circuit layout design includes providing an initial multiple-patterned circuit layout design comprising a first pattern exposure and a second pattern exposure; modifying the initial multiple-patterned circuit layout design by providing a subresolution assist feature to the first pattern exposure; determining whether the presence of any overlapping areas between the subresolution assist feature of the first pattern exposure and the second pattern exposure; and further modifying the initial multiple-patterned circuit layout design by: maintaining the size of any portion of the subresolution assist feature in the overlapping areas; and shrinking the size of any portion of the subresolution assist feature that is not in the overlapping areas.

Abstract: Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict.

Abstract: Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict.

Abstract: Methods for retargeting a via and for fabricating a semiconductor device with a retargeted via are provided. In one embodiment, a method for retargeting a via includes drawing a lower metal layer shape, drawing a via shape for overlying the lower metal layer shape, and drawing an upper metal layer shape for overlying the via shape to create an interconnection area between the via shape and the upper metal layer shape. The method includes determining a potential area loss of the interconnection area during integrated circuit fabrication processing. The method further includes enlarging the via shape to compensate for the potential area loss.

Abstract: Methods for retargeting a via and for fabricating a semiconductor device with a retargeted via are provided. In one embodiment, a method for retargeting a via includes drawing a lower metal layer shape, drawing a via shape for overlying the lower metal layer shape, and drawing an upper metal layer shape for overlying the via shape to create an interconnection area between the via shape and the upper metal layer shape. The method includes determining a potential area loss of the interconnection area during integrated circuit fabrication processing. The method further includes enlarging the via shape to compensate for the potential area loss.