Patents by Inventor Ayrat Galisultanov

Ayrat Galisultanov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230296499
    Abstract: An infrared light source includes an emitting element extending as a radial plane about the emitting element's center and configured to heat up to emit infrared light. The emitting element lies in a cavity bounded by a cover, placed facing the emitting element. The cover has internal and external faces, the internal face facing the emitting element, and the external face defining an interface between the cover and a medium outside the light source. The cover occupies, parallel to a transverse axis perpendicular to the radial plane, a thickness, between the internal and external faces. The external face includes a planar central portion and at least one peripheral portion adjacent and inclined respective to the central portion. The planar central portion extends about the external face's center. In the peripheral portion, the cover's thickness decreases as a function of a distance from the central portion.
    Type: Application
    Filed: October 7, 2021
    Publication date: September 21, 2023
    Inventors: Ayrat Galisultanov, Hélène Duprez
  • Publication number: 20220214272
    Abstract: A device, for emitting and controlling infrared light, comprises a substrate extending between a bottom surface and a top surface. A cavity is provided in the substrate, the cavity opening onto the top surface. A light source extends over the cavity and is able to heat up when passed through by an electric current, so as to emit infrared light. A cover covers the substrate, the cover and the substrate forming a first component enclosing the light source. The light source delineates a first half space comprising the cover, and a second half space comprising the cavity and the bottom surface of the substrate.
    Type: Application
    Filed: May 20, 2020
    Publication date: July 7, 2022
    Inventor: Ayrat Galisultanov
  • Patent number: 10964373
    Abstract: A memory cell in capacitive logic, including a bistable system including a fixed element and a mobile element capable of taking one or the other of two stable positions with respect to the fixed element; a read device including a variable-capacitance capacitor including a first fixed electrode and a second mobile electrode rigidly fixed to the mobile element; and an electrically controllable write device for placing the mobile element in one or the other of its two stable positions.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 30, 2021
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Yann Perrin, Hervé Fanet, Ayrat Galisultanov, Gaël Pillonnet
  • Patent number: 10629382
    Abstract: A system including first and second electric or electronic circuits galvanically isolated from each other, and a coupling device coupling the first circuit to the second circuit, the coupling device including a variable-capacitance capacitor including first and second electrodes mobile with respect to each other, separated by an insulating region, and third and fourth electrodes electrically insulated from the first and second electrodes, capable of receiving a control signal to vary, by an electrostatic, electromagnetic, or piezoelectric actuation mechanism, the relative position of the first and second electrodes, to vary the capacitance between the first and second electrodes.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 21, 2020
    Assignee: Commissariat à l'Ènergie Atomique et aux Ènergies Alternatives
    Inventors: Ayrat Galisultanov, Hervé Fanet, Yann Perrin, Gaël Pillonnet
  • Patent number: 10593485
    Abstract: A logic cell including a fixed assembly including a first electrode, a mobile assembly including a second electrode, and third, fourth, and fifth electrodes, wherein: the first, second, third, fourth, and fifth electrodes are insulated from one another; the first and second electrodes define a capacitor variable according to the position of the mobile assembly relative to the fixed assembly; the third electrode is connected to a node of application of a first logic input signal; the fourth electrode is connected to a node of application of a second logic input signal; the fifth electrode is connected to a reference node; and the position of the second electrode relative to the first electrode is a function of a combination of the first and second logic input signals.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 17, 2020
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Gaël Pillonnet, Yann Perrin, Ayrat Galisultanov, Hervé Fanet
  • Publication number: 20200082867
    Abstract: A memory cell in capacitive logic, including a bistable system including a fixed element and a mobile element capable of taking one or the other of two stable positions with respect to the fixed element; a read device including a variable-capacitance capacitor including a first fixed electrode and a second mobile electrode rigidly fixed to the mobile element; and an electrically controllable write device for placing the mobile element in one or the other of its two stable positions.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 12, 2020
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Yann Perrin, Hervé Fanet, Ayrat Galisultanov, Gaël Pillonnet
  • Publication number: 20190043671
    Abstract: A system including first and second electric or electronic circuits galvanically isolated from each other, and a coupling device coupling the first circuit to the second circuit, the coupling device including a variable-capacitance capacitor including first and second electrodes mobile with respect to each other, separated by an insulating region, and third and fourth electrodes electrically insulated from the first and second electrodes, capable of receiving a control signal to vary, by an electrostatic, electromagnetic, or piezoelectric actuation mechanism, the relative position of the first and second electrodes, to vary the capacitance between the first and second electrodes.
    Type: Application
    Filed: August 2, 2018
    Publication date: February 7, 2019
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Ayrat Galisultanov, Hervé Fanet, Yann Perrin, Gaël Pillonnet
  • Publication number: 20190035559
    Abstract: A logic cell including a fixed assembly including a first electrode, a mobile assembly including a second electrode, and third, fourth, and fifth electrodes, wherein: the first, second, third, fourth, and fifth electrodes are insulated from one another; the first and second electrodes define a capacitor variable according to the position of the mobile assembly relative to the fixed assembly; the third electrode is connected to a node of application of a first logic input signal; the fourth electrode is connected to a node of application of a second logic input signal; the fifth electrode is connected to a reference node; and the position of the second electrode relative to the first electrode is a function of a combination of the first and second logic input signals.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 31, 2019
    Applicant: Commissariat à l'Énergie Atomique etaux Énergies Alternatives
    Inventors: Gaël Pillonnet, Yann Perrin, Ayrat Galisultanov, Hervé Fanet