Abstract: A multi-phase switching power converter includes a panic mode detector that triggers the activation of each phase in an open-loop mode of operation in which an open-loop duty cycle is used that is greater than a closed-loop duty cycle used during closed-loop operation for the active phases.

Abstract: Methods, systems, and devices are described for the implementation of a novel architecture to support a calibrated rate for the transfer of circuit configuration data. Sets of configuration data from a memory may be transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Upon system power-up, there may be a default speed for the transfer of the configuration data. Techniques are described to first transfer calibration data upon power-up; the transferred calibration data may then be used to set an accelerated speed for a remaining portion of the transfer.

Abstract: Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence.

Abstract: A distributed signal multiplexer circuit programmably routes electronic signals. The circuit includes at least two distributor subcircuits. Each distributor subcircuit is configured to connect an input port to an output port through a switch, with a state of each switch being controlled by information received at a control port. The first and second distributor subcircuits are part of a first and second power domain, respectively. The distributed multiplexer circuit also includes an aggregator subcircuit. The aggregator subcircuit is configured to have a first input port connected with the output port of the first distributor subcircuit, a second input port connected to the output port of the second distributor subcircuit, and the output port signal being a signal selected from among the signals received at the input ports of the distributor subcircuits.

Abstract: Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence.

Abstract: Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence.

Abstract: Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence.

Abstract: A distributed signal multiplexer circuit programmably routes electronic signals. The circuit includes at least two distributor subcircuits. Each distributor subcircuit is configured to connect an input port to an output port through a switch, with a state of each switch being controlled by information received at a control port. The first and second distributor subcircuits are part of a first and second power domain, respectively. The distributed multiplexer circuit also includes an aggregator subcircuit. The aggregator subcircuit is configured to have a first input port connected with the output port of the first distributor subcircuit, a second input port connected to the output port of the second distributor subcircuit, and the output port signal being a signal selected from among the signals received at the input ports of the distributor subcircuits.

Abstract: Methods, systems, and devices are described for the implementation of a novel architecture to support a calibrated rate for the transfer of circuit configuration data. Sets of configuration data from a memory may be transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Upon system power-up, there may be a default speed for the transfer of the configuration data. Techniques are described to first transfer calibration data upon power-up; the transferred calibration data may then be used to set an accelerated speed for a remaining portion of the transfer.

Abstract: A method and circuit for performing switching in a frequency timing generator is described. The method includes detecting a request for a new value for a feedback counter or an reference counter, upon which a loading operation is synchronized for the appropriate counter. A time-out order of the feedback counter and the reference counter is determined. Where no time-out order difference is detected therein, a state machine status word function is completed. Where a time-out order difference is detected therein, it is determined which of the reference counter and the feedback counter times out first. Where the reference counter times out first, a constant charge pump current is delivered to a loop filter associated with a phase locked loop to achieve an upward frequency direction. Where the feedback counter times out first, a constant charge pump current is delivered to the loop filter to achieve a downward frequency direction.