Abstract: An array of photon counting phototoreceivers is constructed as an imager with micro-digitized pixels. Each photoreactive comprises a vertical cavity optical amplifier (VCSOA) as an optical amplifier, an avalanche photodiode as detector and an analog-to-digital converter (ADC) in an integrated structure. The ADC serves as a 1-bit digitizer and uses a resonant tunneling bipolar transistor RTBT. While the preferred embodiment of the invention have been described, it will be apparent to those skilled in the art that various modifications may be made to the embodiments without departing from the spirit of the present invention. Such modifications are all within the scope of the present invention.

Abstract: An array of coherent phototoreceivers is constructed as an imager. Each photoreceiver comprises a local oscillator, a detector (mixer), an optical preamplifier (amplifier) and an electronic amplifier (TIA). A vertical cavity optical amplifier (VCSOA) is used either as the mixer or the preamplifier. The optical IF signal can be phase-shifted by 180° and detected to combine with the detected in-phase optical IF signal to obtain a balanced detector. The detector may use an avalanche photodiode with a trans-impedance amplifier for power reduction and higher gain.

Abstract: A vertical cavity semiconductor optical photoamplifer (VCSOA) is used as a modulating retro-reflector (MRR) as a pixel in an array. The boundary of the cavity in the VCSOA forms a mirror for reflecting an incident light as an amplified output.

Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3-10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.

Abstract: An integrated dual wavelength quantum-well infrared photodetector has two absorption peaks of photo response. The structure has a standard quantum well to yield a peak photo response at one wavelength and a sub-well to yield a peak photo response at a second wavelength. The standard quantum well and the sub-well is separated by a barrier. The barrier-well-subwell-well barrier layers are structured periodically. Additional quantum wells and sub-wells may be added to yield a multi-wavelength infrared photodetector.

Abstract: This invention describes an approach for monolithically integrating all the components of a photoreceiver—optical amplifier, optical band-pass filter, and photodiode module—in a single chip. The photoreceiver array employs unique optical amplifier and conversion technologies that provides the ultra-sensitivity required for free space optical communications networks. As an example, by monolithically integrating a vertical cavity surface emitting laser-diode (VCSEL) optical preamplifier with a photodiode receiver and related amplifiers and filters on the same chip, sensitivities as low as ?47 dBm (62 photons/bit at 2.5 Gb/s), along with an order of magnitude reduction in size, weight, and power consumption over comparable commercial-off-the-shelf (COTS) components can be demonstrated.

Abstract: A rotor assembly includes a stack of laminations that are bonded together by a dielectric bonding agent. The laminations and the dielectric bonding agent have matching coefficients of thermal expansion.

Abstract: A rotor assembly includes a stack of laminations that are bonded together by a dielectric bonding agent. The laminations and the dielectric bonding agent have matching coefficients of thermal expansion.

Abstract: A MODFET structure having a semi-insulating substrate overlayed with an undoped semiconductor buffer layer of a first composition. The buffer layer is overlayed with an undoped semiconductor layer having a second composition different from the composition of the buffer layer. An etch stop layer having a composition different from the composition of spacer layer is formed on the spacer layer, which in turn is overlayed with a doped semiconductor layer having the same composition as the spacer layer. A gate well is selectively etched through the doped semiconductor layer using a gate mask and is terminated at the top surface of the etch stop layer. In a first embodiment, a gate electrode is deposited on the surface of the stop layer at the bottom of the gate well. In an alternate embodiment the etch stop layer at the bottom of the gate well is removed and a thin dielectric layer is formed between the spacer layer and the gate electrode.