Abstract: In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.

Abstract: A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.

Abstract: Provided is a magnetic domain wall displacement memory cell, including a recording layer including a magnetic film, the recording layer including: a magnetization reversal region in which magnetization is reversible; and first and second magnetization fixed regions that supply a spin-polarized electron to the magnetization reversal region. The magnetic domain wall displacement memory cell is configured so that a first region in which magnetization reversal occurs due to a first current flowing in a direction parallel to a film surface of the recording layer and a first magnetic field component in the direction parallel to the film surface of the recording layer is formed, and a second region in which no magnetization reversal occurs is formed.

Abstract: A semiconductor integrated circuit (100) comprising: a plurality of processing circuits (11, 12, 13) each including a notification units for outputting a notification signal according to the processing state of the own processing circuit; a plurality of power supply switch units (SW1, SW2, SW3) for switching the connection states between the respective processing circuits and a power supply source; a power supply switch control circuit which is connected with the notification means (111, 121, 131), stores power supply control information (101) including a plurality of connection statuses, and controls the connection states on the basis of the notification signals and the power supply control information; and a data bus (BS) and the like connecting each of the processing circuits and the power supply switch control circuit, wherein: at least two or more of the plurality of processing circuits update the power supply control information via the data bus and the like before outputting a notification signal; and

Abstract: A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.

Abstract: Provided is a magnetic domain wall displacement memory cell, including a recording layer including a magnetic film, the recording layer including: a magnetization reversal region in which magnetization is reversible; and first and second magnetization fixed regions that supply a spin-polarized electron to the magnetization reversal region. The magnetic domain wall displacement memory cell is configured so that a first region in which magnetization reversal occurs due to a first current flowing in a direction parallel to a film surface of the recording layer and a first magnetic field component in the direction parallel to the film surface of the recording layer is formed, and a second region in which no magnetization reversal occurs is formed.

Abstract: A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.

Abstract: A semiconductor integrated circuit includes a plurality of first non-volatile registers including a retention circuit that retains volatile data and one or more non-volatile elements capable of retaining non-volatile data, and a second non-volatile register that retains a load enable bit that decides in which one of the plurality of first non-volatile registers data is loaded. The semiconductor integrated circuit also includes a non-volatile register control circuit that, when supply power is delivered from outside, loads to the retention circuit data retained by the non-volatile element(s) contained in the first non-volatile register specified by the load enable bit loaded from the second non-volatile register (FIG. 1).

Abstract: A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.

Abstract: A variable resistance element includes a first conductive portion; an insulating film pattern provided on the first conductive portion; a level difference with respect to the upper surface of the first conductive portion, the level difference being formed of the insulating film pattern; a variable resistance film provided on a side surface of the level difference and having contact with the upper surface of the first conductive portion on the lower-end side of the side surface of the level difference; and a second conductive portion having contact with the variable resistance film on the upper-end side of the side surface of the level difference.

Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.

Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.