Abstract: An operational amplifier that decreases idling current, widens a voltage output range, and increases load driving capacity. The operational amplifier includes a first output transistor connected to a high potential power supply. A second output transistor is connected between the first output transistor and a low potential power supply. The first and second output transistors generate an output signal at a node between the first output transistor and the second output transistor. An idling current control circuit controls the collector current of the first output transistor in accordance with the base voltage of the second output transistor to control the idling current of the first and second output transistors.

Abstract: An operational amplifier that decreases idling current, widens a voltage output range, and increases load driving capacity. The operational amplifier includes a first output transistor connected to a high potential power supply. A second output transistor is connected between the first output transistor and a low potential power supply. The first and second output transistors generate an output signal at a node between the first output transistor and the second output transistor. An idling current control circuit controls the collector current of the first output transistor in accordance with the base voltage of the second output transistor to control the idling current of the first and second output transistors.

Abstract: An operational amplifier that decreases idling current, widens a voltage output range, and increases load driving capacity. The operational amplifier includes a first output transistor connected to a high potential power supply. A second output transistor is connected between the first output transistor and a low potential power supply. The first and second output transistors generate an output signal at a node between the first output transistor and the second output transistor. An idling current control circuit controls the collector current of the first output transistor in accordance with the base voltage of the second output transistor to control the idling current of the first and second output transistors.

Abstract: An operational amplifier for increasing the response speed of its output voltage relative to an input signal while increasing the tolerable amplitude of the output voltage. The operational amplifier includes a PNP output transistor connected to a high potential power supply, an NPN output transistor connected between the PNP output transistor and a low potential power supply, and a drive unit, which drives each output transistor in accordance with an input current. The drive unit includes a current source, a first current mirror circuit, and a second mirror circuit. The input current is supplied to a node between the first and second current mirror circuits. The base of the NPN output transistor is connected to the node, and the base of the PNP output transistor is connected to a further node between the current source and the first current mirror circuit.

Abstract: A peak hold circuit which improves the precision of a hold voltage. The peak hold circuit includes a first input transistor which receives an input voltage and a second input transistor which receives the hold voltage. The peak hold circuit further includes a hold capacitor, a hold-voltage setting transistor and a bypass circuit. The hold capacitor supplies the hold voltage to the second input transistor. The hold-voltage setting transistor receives base current from the collector of the first input transistor and makes the hold voltage coincide with the input voltage in accordance with the base current. The bypass circuit bypasses bias current to be supplied to the second input transistor when the hold-voltage setting transistor is turned off.

Abstract: An operational amplifier for increasing the response speed of its output voltage relative to an input signal while increasing the tolerable amplitude of the output voltage. The operational amplifier includes a PNP output transistor connected to a high potential power supply, an NPN output transistor connected between the PNP output transistor and a low potential power supply, and a drive unit, which drives each output transistor in accordance with an input current. The drive unit includes a current source, a first current mirror circuit, and a second mirror circuit. The input current is supplied to a node between the first and second current mirror circuits. The base of the NPN output transistor is connected to the node, and the base of the PNP output transistor is connected to a further node between the current source and the first current mirror circuit.

Abstract: A peak hold circuit which improves the precision of a hold voltage. The peak hold circuit includes a first input transistor which receives an input voltage and a second input transistor which receives the hold voltage. The peak hold circuit further includes a hold capacitor, a hold-voltage setting transistor and a bypass circuit. The hold capacitor supplies the hold voltage to the second input transistor. The hold-voltage setting transistor receives base current from the collector of the first input transistor and makes the hold voltage coincide with the input voltage in accordance with the base current. The bypass circuit bypasses bias current to be supplied to the second input transistor when the hold-voltage setting transistor is turned off.

Abstract: An operational amplifier that decreases idling current, widens a voltage output range, and increases load driving capacity. The operational amplifier includes a first output transistor connected to a high potential power supply. A second output transistor is connected between the first output transistor and a low potential power supply. The first and second output transistors generate an output signal at a node between the first output transistor and the second output transistor. An idling current control circuit controls the collector current of the first output transistor in accordance with the base voltage of the second output transistor to control the idling current of the first and second output transistors.