Abstract: A test method of the present disclosure includes: applying a thermal grease on a support plate; placing a press plate such that the press plate faces the support plate with the thermal grease interposed between the press plate and the support plate; changing a distance between the support plate and the press plate; and observing a shape of the thermal grease after the distance between the support plate and the press plate is changed. The pumping-out performance is determined based on the shape of the thermal grease.

Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.

Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.

Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.

Abstract: A photomask is provided which can have a large depth of focus even if four main features are annularly arranged at random. The photomask has four annularly arranged main features based on design information of a circuit feature to be formed on a wafer, and a sub-feature is laid at an intersection point of two diagonal lines of a quadrangle formed by four vertices inside the four main features in order to increase a depth of focus of an exposure feature. Therefore, the depth of focus can be increased even if the main features are not arranged at a constant pitch.

Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.

Abstract: A photomask is provided which can have a large depth of focus even if four main features are annularly arranged at random. The photomask has four annularly arranged main features based on design information of a circuit feature to be formed on a wafer, and a sub-feature is laid at an intersection point of two diagonal lines of a quadrangle formed by four vertices inside the four main features in order to increase a depth of focus of an exposure feature. Therefore, the depth of focus can be increased even if the main features are not arranged at a constant pitch.

Abstract: A photomask is disclosed which can suppress deterioration of the depth of focus even in the case where main features are arranged randomly. Sub-features are replaced by a quadrangular sub-feature located inside an external quadrangle which includes as part of its outer periphery the outermost portions of the original sub-features. The sub-feature after the replacement is preferably in a square shape and the length of one side thereof is determined in accordance with the length of the associated external quadrangle. A central position of the sub-feature after the replacement is preferably coincident with the center of the external quadrangle or the center of gravity of the region which includes the original sub-features.

Abstract: A photomask is disclosed which can suppress deterioration of the depth of focus even in the case where main features are arranged randomly. Sub-features are replaced by a quadrangular sub-feature located inside an external quadrangle which includes as part of its outer periphery the outermost portions of the original sub-features. The sub-feature after the replacement is preferably in a square shape and the length of one side thereof is determined in accordance with the length of the associated external quadrangle. A central position of the sub-feature after the replacement is preferably coincident with the center of the external quadrangle or the center of gravity of the region which includes the original sub-features.

Abstract: An organic ARC film is formed on a semiconductor substrate. A resist is applied to the organic ARC film and exposure and development processes are carried out, thereby a predetermined resist pattern is formed. This resist pattern is used as a mask so as to carry out, on the exposed organic ARC film, a dry etching process for a period of time of approximately 15 seconds using a gas including, thereby the organic ARC film is removed so as to expose the surface of the semiconductor substrate. Next, predetermined impurity ions are implanted into the semiconductor substrate using the resist pattern and the organic ARC film located directly beneath this resist pattern as a mask, thereby an impurity region is formed in the surface of the exposed semiconductor substrate. Thereby, implantation treatment and wet etching treatment can be carried out without fail using the resist pattern as a mask.

Abstract: A resist pattern, containing a material capable of generating an acid by exposure to light, is covered with a resist containing a material capable of crosslinkage in the presence of an acid. The acid is generated in the resist pattern by application of heat or by exposure to light, and a crosslinked layer is formed at the interface as a cover layer for the resist pattern, thereby causing the resist pattern to be thickened. Thus, the hole diameter of the resist pattern can be reduced, or the isolation width of a resist pattern can be reduced.

Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

Abstract: An improved method of forming a resist pattern permitting control of a resist profile of a chemically amplified-type resist is provided. A chemically amplified-type resist is exposed to light using a mask. The resist is then baked by PEB at a first temperature, and developed halfway. The resist is baked again at a second temperature lower than the first temperature, and then fully developed. A resist pattern is thus obtained.

Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

Abstract: A first resist pattern, which is capable of generating an acid, is formed on a semiconductor device layer. Over the first resist pattern, a layer of a second resist, which is capable of undergoing an cross-linking reaction in the presence of an acid, is formed. Then, a cross-linked film is formed in portions of said layer of the second resist at the boundary with said first resist by action of an acid from said first resist. Thereafter, non-cross-linked portions of said second resist are removed to form a finely isolated resist pattern. The semiconductor device layer is etched, via a mask of said finely isolated resist pattern, to form a fine spaces or holes.