Abstract: According to one embodiment, in a semiconductor storage device, a plurality of second pillars each includes a first sub-pillar that is a single substance of a first insulating layer extending in the stacking direction in a lower layer side of a stacked body and a second sub-pillar arranged at a height position in an upper layer side of the stacked body to correspond to the first sub-pillar. The second sub-pillar includes a semiconductor layer extending in the stacking direction at the height position in the upper layer side of the stacked body, a second insulating layer covering a sidewall of the semiconductor layer, a third insulating layer covering a sidewall of the second insulating layer, and a fourth insulating layer that includes a different material from the second and third insulating layers and is interposed between the second and third insulating layers.

Abstract: A memory device includes a first chip including a first electrode and a second chip including a second electrode. The first electrode includes a first conductive film having a first surface in contact with the second electrode at a boundary region of the first and second electrodes, a second surface spaced apart from the boundary region, and a third surface between the first surface and the second surface, and having a first portion on the first surface side and a second portion on the second surface side, and includes a second conductive film covering the second surface and the third surface of the first conductive film. A (111) orientation ratio of copper contained in the first portion is higher than a (111) orientation ratio of copper contained in the second portion.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.

Abstract: A semiconductor memory device according to an embodiment includes: a first stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the first stacked body including a stair portion processed into a stair shape extending in a first direction such that the plurality of conductive layers forms terrace surfaces; an insulating film covering an upper portion of the first stacked body including the stair portion; and a first plate-like portion that extends in the first direction in the stair portion and penetrates the first stacked body, the first plate-like portion including a plurality of bridge portions that are arranged locally on an upper end portion side and intermittently in the first direction to couple parts of the insulating film arranged on both sides of the first plate-like portion to each other.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.