Patents by Inventor Ayumi Yokozawa

Ayumi Yokozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5933367
    Abstract: A control gate is loaded with a negative voltage pulse and a source region is loaded with a positive constant voltage pulse while a drain region is at a floating state. More specifically, the absolute value of the voltage applied to the control gate is increased with time for a period from the start of a memory erasing action (the application of the pulse voltage) to 2 msec and then remains constant from 2 msec to the end of the memory erasing action. As the result, a potential difference between the source region and the control gate at the start of the memory erasing action is smaller than that at the end of the memory erasing action. This prevents the tunnel oxide layer from receiving a high electric field stress at the start of the memory erasing action, thus improving the write/erase endurance.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: August 3, 1999
    Assignee: NEC Corporation
    Inventors: Makoto Matsuo, Ayumi Yokozawa
  • Patent number: 5886905
    Abstract: On determining operating conditions for a nonvolatile semiconductor memory including a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), measurement is made, before completion of manufacture of the nonvolatile semiconductor memory and after completion of manufacture of the MOSFET, of characteristics of the MOSFET to obtain parameters which are used in simulating an operation of the nonvolatile semiconductor memory. By using the parameters, simulation of the operation of the nonvolatile semiconductor memory is executed to obtain a simulation result which is preferably a result relating to deterioration of operation characteristics of the nonvolatile semiconductor memory. The operating conditions for the nonvolatile semiconductor memory are obtained from the simulation result. The nonvolatile semiconductor memory may be an EEPROM (Electrically Erasable Programmable Read-Only Memory).
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: March 23, 1999
    Assignee: NEC Corporation
    Inventor: Ayumi Yokozawa
  • Patent number: 5663087
    Abstract: The present invention provides a method for forming a silicon nitride film used for a capacitor dielectric film on a silicon substrate and a poly-silicon layer which comprises steps of forming a first thin silicon nitride film by a rapid thermal nitrogen process and forming a second silicon nitride film on the first thin silicon nitride film to a required thickness by LPCVD. In the LPCVD, a gas which reduces surface reactions is introduced to a growing surface of the silicon nitride film by a means different from a means supplying starting material gases of the silicon nitride film, so as to improve a break down voltage and leakage current of the capacitor silicon nitride film.
    Type: Grant
    Filed: September 21, 1994
    Date of Patent: September 2, 1997
    Assignee: NEC Corporation
    Inventor: Ayumi Yokozawa
  • Patent number: 5590051
    Abstract: A process simulation method and a process simulator are disclosed wherein a simulation for optimum process conditions for formation of a dielectric film for a capacitor by a chemical vapor deposition method is executed using a non-empirical reaction model.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: December 31, 1996
    Assignee: NEC Corporation
    Inventor: Ayumi Yokozawa