Patents by Inventor Ayumu Sato
Ayumu Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9120776Abstract: The present invention provides a fused heterocyclic compound having an ROR?t inhibitory action. The present invention relates to a compound represented by the formula (I?): wherein each symbol is as defined in the specification, provided that 2-(2-((4-cyanophenyl)amino)-2-oxoethoxy)-N-(9-ethyl-9H-carbazol-3-yl)acetamide and N-(4-cyanophenyl)-N?-(9-ethyl-9H-carbazol-3-yl)-3-methylpentanediamide are excluded, or a thereof.Type: GrantFiled: September 21, 2012Date of Patent: September 1, 2015Assignee: Takeda Pharmaceutical Company LimitedInventors: Satoshi Yamamoto, Junya Shirai, Yoshiyuki Fukase, Yoshihide Tomata, Ayumu Sato, Atsuko Ochida, Kazuko Yonemori, Hideyuki Nakagawa
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Patent number: 9117590Abstract: A laminated ceramic electronic component has electrode layers stacked with ceramic layers, where the thickness of each electrode layer is controlled to 0.5 ?m or less and the average size of crystal grains constituting the electrode layer is controlled to 0.1 ?m or less. The occurrence of structural defects in the laminated ceramic electronic component can be suppressed and high continuity of the electrode layers stacked with the ceramic layers is ensured.Type: GrantFiled: June 19, 2013Date of Patent: August 25, 2015Assignee: TAIYO YUDEN CO., LTD.Inventors: Yukihiro Konishi, Yusuke Kowase, Kazumichi Hiroi, Kotaro Mizuno, Ayumu Sato
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Publication number: 20150179681Abstract: A semiconductor device includes: a transistor having an oxide semiconductor film; and a retention capacitor having a first conductive film and a second conductive film, the first conductive film containing an oxide material and being in contact with the oxide semiconductor film, and the second conductive film facing the first conductive film with an insulating film in between.Type: ApplicationFiled: November 25, 2014Publication date: June 25, 2015Inventor: Ayumu Sato
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Publication number: 20150162399Abstract: A semiconductor device includes: a retention capacitor having an oxide semiconductor film and a conductive film with an insulating film in between; and a metal film provided to be in contact with a surface of the oxide semiconductor film opposed to a surface facing the conductive film, the metal film being at least partially oxidized.Type: ApplicationFiled: October 9, 2014Publication date: June 11, 2015Applicant: SONY CORPORATIONInventor: Ayumu Sato
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Patent number: 8946104Abstract: A dielectric ceramic whose primary component is an ABO3 compound (A contains Ba and B contains Ti) has a per-layer thickness of approx. 0.5 ?m or less, where the volume ratio to all dielectric sintered grains of those whose grain size is in a range of 0.02 ?m to 0.15 ?m is adjusted to a grain size distribution of 1% to 10%. High dielectric constant and high reliability can be achieved at the same time with the dielectric ceramic.Type: GrantFiled: June 19, 2013Date of Patent: February 3, 2015Assignee: Taiyo Yuden Co., Ltd.Inventors: Yukihiro Konishi, Yusuke Kowase, Kazumichi Hiroi, Kotaro Mizuno, Ayumu Sato
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Publication number: 20140291639Abstract: Provided is a semiconductor device that includes: a transistor; an oxide semiconductor film; a first conductive film electrically connected to the oxide semiconductor film; and a first insulating film provided between the first conductive film and the oxide semiconductor film.Type: ApplicationFiled: March 10, 2014Publication date: October 2, 2014Applicant: Sony CorporationInventors: Yasuhiro TERAI, Takahide ISHII, Ayumu SATO
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Publication number: 20140268879Abstract: A waveguide light diffuser panel is disclosed that diffuses source lights and transmits ambient light. Conventional waveguide light diffusers diffuse all light and therefore provide a hazy outcome. In manufacturing a waveguide transparent diffuser, a printing method, such as inkjet printing, may be used. In this method, dot micro-lenses are formed on one side of a panel, which cover a portion of the panel in a staggered or random arrangement. The other side of the panel is coated with an anti-reflective material, or the shape of the panel may be concave. The dot shape is designed for efficient reflection of the incident light, as opposed to conventional hazy diffusers in which the reflection efficiency is low. High reflection efficiency in this case compensates for the reduced dot coverage.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: PANASONIC CORPORATIONInventors: Yosuke MIZUYAMA, Nathan HARRISON, Ayumu SATO
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Publication number: 20140228409Abstract: The present invention provides a fused heterocyclic compound having an ROR?t inhibitory action. The present invention relates to a compound represented by the formula (I?): wherein each symbol is as defined in the specification, provided that 2-(2-((4-cyanophenyl)amino)-2-oxoethoxy)-N-(9-ethyl-9H-carbazol-3-yl)acetamide and N-(4-cyanophenyl)-N?-(9-ethyl-9H-carbazol-3-yl)-3-methylpentanediamide are excluded, or a salt thereof.Type: ApplicationFiled: September 21, 2012Publication date: August 14, 2014Inventors: Satoshi Yamamoto, Junya Shirai, Yoshiyuki Fukase, Yoshihide Tomata, Ayumu Sato, Atsuko Ochida, Kazuko Yonemori, Hideyuki Nakagawa
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Publication number: 20140163001Abstract: Provided is a heterocyclic compound having an ROR?t inhibitory activity.Type: ApplicationFiled: July 27, 2012Publication date: June 12, 2014Applicant: Takeda Pharmaceutical Company LimitedInventors: Satoshi Yamamoto, Junya Shirai, Atsuko Ochida, Yoshiyuki Fukase, Yoshihide Tomata, Ayumu Sato, Shotaro Miura, Kazuko Yonemori, Ryokichi Koyama
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Patent number: 8624240Abstract: Provided is a top gate thin film transistor, including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.Type: GrantFiled: July 21, 2011Date of Patent: January 7, 2014Assignee: Canon Kabushiki KaishaInventors: Ayumu Sato, Hideya Kumomi, Hisato Yabuta, Ryo Hayashi, Yasuyoshi Takai
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Publication number: 20130342956Abstract: A laminated ceramic electronic component has electrode layers stacked with ceramic layers, where the thickness of each electrode layer is controlled to 0.5 ?m or less and the average size of crystal grains constituting the electrode layer is controlled to 0.1 ?m or less. The occurrence of structural defects in the laminated ceramic electronic component can be suppressed and high continuity of the electrode layers stacked with the ceramic layers is ensured.Type: ApplicationFiled: June 19, 2013Publication date: December 26, 2013Inventors: Yukihiro KONISHI, Yusuke KOWASE, Kazumichi HIROI, Kotaro MIZUNO, Ayumu SATO
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Publication number: 20130342957Abstract: A dielectric ceramic whose primary component is an ABO3 compound (A contains Ba and B contains Ti) has a per-layer thickness of approx. 0.5 ?m or less, where the volume ratio to all dielectric sintered grains of those whose grain size is in a range of 0.02 ?m to 0.15 ?m is adjusted to a grain size distribution of 1% to 10%. High dielectric constant and high reliability can be achieved at the same time with the dielectric ceramic.Type: ApplicationFiled: June 19, 2013Publication date: December 26, 2013Inventors: Yukihiro KONISHI, Yusuke KOWASE, Kazumichi HIROI, Kotaro MIZUNO, Ayumu SATO
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Publication number: 20130316521Abstract: The present invention provides a method for producing a silicon wafer including a step of, after growing the oxide film on one surface of a raw material silicon wafer by chemical-vapor deposition, performing double-side polishing of the raw material silicon wafer in such a manner that a suede polishing pad or a velour polishing pad with an asker-C rubber hardness of 50° or more but less than 90° is used for the oxide-film surface.Type: ApplicationFiled: February 9, 2012Publication date: November 28, 2013Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Takuya Sasaki, Hiromasa Hashimoto, Kazuya Sato, Ayumu Sato
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Patent number: 8502217Abstract: Provided is an oxide semiconductor device including an oxide semiconductor layer and an insulating layer coming into contact with the oxide semiconductor layer in which the insulating layer includes: a first insulating layer coming into contact with an oxide semiconductor, having a thickness of 50 nm or more, and including an oxide containing Si and O; a second insulating layer coming into contact with the first insulating layer, having a thickness of 50 nm or more, and including a nitride containing Si and N; and a third insulating layer coming into contact with the second insulating layer, the first insulating layer and the second insulating layer having hydrogen contents of 4×1021 atoms/cm3 or less, and the third insulating layer having a hydrogen content of more than 4×1021 atoms/cm3.Type: GrantFiled: November 27, 2008Date of Patent: August 6, 2013Assignee: Canon Kabushiki KaishaInventors: Ayumu Sato, Ryo Hayashi, Hisato Yabuta, Tomohiro Watanabe
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Patent number: 8481569Abstract: The present invention aims to provide an iminopyridine derivative compound having an ?1Dadrenergic receptor antagonistic action, which is useful as an agent for the prophylaxis or treatment of a lower urinary tract disease and the like. The present invention provides a compound represented by the formula wherein each symbol is as defined in the specification, or a salt thereof.Type: GrantFiled: October 7, 2010Date of Patent: July 9, 2013Assignee: Takeda Pharmaceutical Company LimitedInventors: Masato Yoshida, Nobuki Sakauchi, Ayumu Sato
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Patent number: 8445902Abstract: Provided are a coplanar structure thin film transistor that allows a threshold voltage to change only a little under electric stress, and a method of manufacturing the same. The thin film transistor includes on a substrate at least: a gate electrode; a gate insulating layer; an oxide semiconductor layer including a source electrode, a drain electrode, and a channel region; a channel protection layer; and an interlayer insulating layer. The channel protection layer includes one or more layers, the layer in contact with the oxide semiconductor layer among the one or more layers being made of an insulating material containing oxygen, ends of the channel protection layer are thinner than a central part of the channel protection layer, the interlayer insulating layer contains hydrogen, and regions of the oxide semiconductor layer that are in direct contact with the interlayer insulating layer form the source electrode and the drain electrode.Type: GrantFiled: April 28, 2009Date of Patent: May 21, 2013Assignee: Canon Kabushiki KaishaInventors: Ayumu Sato, Ryo Hayashi, Hisato Yabuta, Masafumi Sano
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Patent number: 8344373Abstract: To achieve, in an oxide semiconductor thin layer transistor, both the stability of threshold voltage against electric stress and suppression of variation in the threshold voltage in a transfer characteristic. A thin film transistor includes an oxide semiconductor layer and a gate insulating layer disposed so as to be in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer contains hydrogen atoms and includes at least two regions that function as active layers of the oxide semiconductor and have different average hydrogen concentrations in the layer thickness direction; and when the regions functioning as the active layers of the oxide semiconductor are sequentially defined as, from the side of the gate insulating layer, a first region and a second region, the average hydrogen concentration of the first region is lower than the average hydrogen concentration of the second region.Type: GrantFiled: September 27, 2010Date of Patent: January 1, 2013Assignee: Canon Kabushiki KaishaInventors: Ayumu Sato, Hideya Kumomi, Ryo Hayashi, Tomohiro Watanabe
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Publication number: 20120032173Abstract: Provided is a top gate thin film transistor, including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.Type: ApplicationFiled: July 21, 2011Publication date: February 9, 2012Applicant: CANON KABUSHIKI KAISHAInventors: Ayumu Sato, Hideya Kumomi, Hisato Yabuta, Ryo Hayashi, Yasuyoshi Takai
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Publication number: 20110073856Abstract: To achieve, in an oxide semiconductor thin layer transistor, both the stability of threshold voltage against electric stress and suppression of variation in the threshold voltage in a transfer characteristic. A thin film transistor includes an oxide semiconductor layer and a gate insulating layer disposed so as to be in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer contains hydrogen atoms and includes at least two regions that function as active layers of the oxide semiconductor and have different average hydrogen concentrations in the layer thickness direction; and when the regions functioning as the active layers of the oxide semiconductor are sequentially defined as, from the side of the gate insulating layer, a first region and a second region, the average hydrogen concentration of the first region is lower than the average hydrogen concentration of the second region.Type: ApplicationFiled: September 27, 2010Publication date: March 31, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Ayumu Sato, Hideya Kumomi, Ryo Hayashi, Tomohiro Watanabe
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Publication number: 20110042670Abstract: Provided are a coplanar structure thin film transistor that allows a threshold voltage to change only a little under electric stress, and a method of manufacturing the same. The thin film transistor includes on a substrate at least: a gate electrode; a gate insulating layer; an oxide semiconductor layer including a source electrode, a drain electrode, and a channel region; a channel protection layer; and an interlayer insulating layer. The channel protection layer includes one or more layers, the layer in contact with the oxide semiconductor layer among the one or more layers being made of an insulating material containing oxygen, ends of the channel protection layer are thinner than a central part of the channel protection layer, the interlayer insulating layer contains hydrogen, and regions of the oxide semiconductor layer that are in direct contact with the interlayer insulating layer form the source electrode and the drain electrode.Type: ApplicationFiled: April 28, 2009Publication date: February 24, 2011Applicant: Canon Kabushiki KaishaInventors: Ayumu Sato, Ryo Hayashi, Hisato Yabuta, Masafumi Sano