Patents by Inventor Ayumu Tsujimura
Ayumu Tsujimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9563403Abstract: A random number generating device of the present disclosure includes: an arithmetic random number generator that generates an arithmetic random number sequence; an arithmetic random number converter that sequentially reads at least one arithmetic random number from the arithmetic random number sequence and converts a value of the read arithmetic random number into a voltage or current value of at least two predetermined levels of gray scale having an identical polarity; a hysteresis unit that outputs values depending on a presently-input voltage or current value and a previously-input voltage or current value with respect to the sequentially-input voltage or current value; and a threshold processor that binarizes the output of the hysteresis unit.Type: GrantFiled: December 12, 2014Date of Patent: February 7, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Michihito Ueda, Yu Nishitani, Yukihiro Kaneko, Ayumu Tsujimura
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Publication number: 20150100614Abstract: A random number generating device of the present disclosure includes: an arithmetic random number generator that generates an arithmetic random number sequence; an arithmetic random number converter that sequentially reads at least one arithmetic random number from the arithmetic random number sequence and converts a value of the read arithmetic random number into a voltage or current value of at least two predetermined levels of gray scale having an identical polarity; a hysteresis unit that outputs values depending on a presently-input voltage or current value and a previously-input voltage or current value with respect to the sequentially-input voltage or current value; and a threshold processor that binarizes the output of the hysteresis unit.Type: ApplicationFiled: December 12, 2014Publication date: April 9, 2015Inventors: MICHIHITO UEDA, YU NISHITANI, YUKIHIRO KANEKO, AYUMU TSUJIMURA
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Patent number: 7160748Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: GrantFiled: February 24, 2005Date of Patent: January 9, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Patent number: 7108745Abstract: After a Group III-V compound semiconductor layer, to which a p-type dopant has been introduced, has been formed over a substrate, the compound semiconductor layer is annealed. In the stage of heating the compound semiconductor layer, atoms, deactivating the p-type dopant, are eliminated from the compound semiconductor layer by creating a temperature gradient in the compound semiconductor layer.Type: GrantFiled: April 16, 2003Date of Patent: September 19, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiaki Hasegawa, Ayumu Tsujimura, Isao Kidoguchi, Yuzaburo Ban
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Patent number: 6940100Abstract: A semiconductor light-emitting device of Group III-V compound semiconductors includes a quantum well layer, which is formed over a substrate and includes a barrier layer and a well layer that are alternately stacked one upon the other. The band gap of the well layer is narrower than that of the barrier layer. The well layer contains indium and nitrogen, while the barrier layer contains aluminum and nitrogen. In this structure, a tensile strain is induced in the barrier layer, and therefore, a compressive strain induced in the quantum well layer can be reduced. As a result, a critical thickness, at which pits are created, can be increased.Type: GrantFiled: January 3, 2003Date of Patent: September 6, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ayumu Tsujimura, Yoshiaki Hasegawa, Akihiko Ishibashi, Isao Kidoguchi, Yuzaburo Ban, Masakatsu Suzuki
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Patent number: 6921678Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: GrantFiled: May 9, 2003Date of Patent: July 26, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Publication number: 20050142682Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: ApplicationFiled: February 24, 2005Publication date: June 30, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Patent number: 6911351Abstract: The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0?u, v, w?1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0?x, y, z?1 and x+y+z=1, by using, as a seed crystal, C planes corresponding to top faces of the convexes exposed from the mask film.Type: GrantFiled: January 16, 2003Date of Patent: June 28, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Isao Kidoguchi, Akihiko Ishibashi, Ryoko Miyanaga, Gaku Sugahara, Masakatsu Suzuki, Masahiro Kume, Yuzaburo Ban, Kiyoyuki Morita, Ayumu Tsujimura, Yoshiaki Hasegawa
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Patent number: 6858877Abstract: A facet-forming layer made of nitride semiconductor containing at least aluminum is formed on a substrate made of gallium nitride (GaN). A facet surface inclined with respect to a C-surface is formed on the surface of the facet-forming layer, and a selective growth layer laterally grows from the inclined facet surface. As a result, the selective growth layer can substantially lattice-match an n-type cladding layer made of n-type AlGaN and grown on the selective growth layer. For example, a laser structure without cracks being generated can be obtained by crystal growth.Type: GrantFiled: January 28, 2003Date of Patent: February 22, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasutoshi Kawaguchi, Akihiko Ishibashi, Ayumu Tsujimura, Nobuyuki Otsuka
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Patent number: 6777253Abstract: The method for fabricating a semiconductor includes the steps of: (1) growing a first semiconductor layer made of AlxGa1−xN (0≦x≦1) on a substrate at a temperature higher than room temperature; and (2) growing a second semiconductor layer made of AluGavInwN (0<u≦1, 0≦v≦1, 0≦w≦1, u+v+w=1) over the first semiconductor layer. In the step (1), the mole fraction x of Al of the first semiconductor layer is set so that the lattice constant of the first semiconductor layer at room temperature substantially matches with the lattice constant of the second semiconductor layer in the bulk state after thermal shrinkage or thermal expansion.Type: GrantFiled: December 18, 2001Date of Patent: August 17, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yasutoshi Kawaguchi, Nobuyuki Otsuka, Kiyoshi Ohnaka
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Patent number: 6764871Abstract: A method for fabricating a nitride semiconductor device comprising steps of forming a low-temperature deposited layer composed of a Group III-Group V nitride semiconductor containing at least Al onto a surface of substrate (101) at a first temperature; subjecting the low-temperature deposited layer to heat treatment at a second temperature, which is higher than the first temperature, and converting the low-temperature deposited layer into a faceted layer (102); initially growing a GaN based semiconductor layer (103) onto a surface of the faceted layer at a third temperature; and fully growing the GaN based semiconductor layer at a fourth temperature that is lower than the third temperature. By employing the method for fabricating a nitride semiconductor device according to the present invention, it is possible to provide a nitride semiconductor device with high quality and high reliability.Type: GrantFiled: June 20, 2003Date of Patent: July 20, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasutoshi Kawaguchi, Akihiko Ishibashi, Ayumu Tsujimura
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Patent number: 6720586Abstract: The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0≦u, v, w ≦1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0≦x, y, z≦1 and x+y+z=1, by using, as a seed crystal, Cplanes corresponding to top faces of the convexes exposed from the mask film.Type: GrantFiled: November 15, 2000Date of Patent: April 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Isao Kidoguchi, Akihiko Ishibashi, Ryoko Miyanaga, Gaku Sugahara, Masakatsu Suzuki, Masahiro Kume, Yuzaburo Ban, Kiyoyuki Morita, Ayumu Tsujimura, Yoshiaki Hasegawa
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Publication number: 20030232457Abstract: A method for fabricating a nitride semiconductor device comprising steps of forming a low-temperature deposited layer composed of a Group III-Group V nitride semiconductor containing at least Al onto a surface of substrate (101) at a first temperature; subjecting the low-temperature deposited layer to heat treatment at a second temperature, which is higher than the first temperature, and converting the low-temperature deposited layer into a faceted layer (102); initially growing a GaN based semiconductor layer (103) onto a surface of the faceted layer at a third temperature; and fully growing the GaN based semiconductor layer at a fourth temperature that is lower than the third temperature. By employing the method for fabricating a nitride semiconductor device according to the present invention, it is possible to provide a nitride semiconductor device with high quality and high reliability.Type: ApplicationFiled: June 20, 2003Publication date: December 18, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yasutoshi Kawaguchi, Akihiko Ishibashi, Ayumu Tsujimura
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Publication number: 20030209192Abstract: After a Group III-V compound semiconductor layer, to which a p-type dopant has been introduced, has been formed over a substrate, the compound semiconductor layer is annealed. In the stage of heating the compound semiconductor layer, atoms, deactivating the p-type dopant, are eliminated from the compound semiconductor layer by creating a temperature gradient in the compound semiconductor layer.Type: ApplicationFiled: April 16, 2003Publication date: November 13, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiaki Hasegawa, Ayumu Tsujimura, Isao Kidoguchi, Yuzaburo Ban
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Publication number: 20030203629Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a-first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: ApplicationFiled: May 9, 2003Publication date: October 30, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Publication number: 20030183827Abstract: A facet-forming layer made of nitride semiconductor containing at least aluminum is formed on a substrate made of gallium nitride (GaN). A facet surface inclined with respect to a C-surface is formed on the surface of the facet-forming layer, and a selective growth layer laterally grows from the inclined facet surface. As a result, the selective growth layer can substantially lattice-match an n-type cladding layer made of n-type AlGaN and grown on the selective growth layer. For example, a laser structure without cracks being generated can be obtained by crystal growth.Type: ApplicationFiled: January 28, 2003Publication date: October 2, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yasutoshi Kawaguchi, Akihiko Ishibashi, Ayumu Tsujimura, Nobuyuki Otsuka
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Publication number: 20030168653Abstract: A semiconductor light-emitting device of Group III-V compound semiconductors includes a quantum well layer, which is formed over a substrate and includes a barrier layer and a well layer that are alternately stacked one upon the other. The band gap of the well layer is narrower than that of the barrier layer. The well layer contains indium and nitrogen, while the barrier layer contains aluminum and nitrogen. In this structure, a tensile strain is induced in the barrier layer, and therefore, a compressive strain induced in the quantum well layer can be reduced. As a result, a critical thickness, at which pits are created, can be increased.Type: ApplicationFiled: January 3, 2003Publication date: September 11, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Ayumu Tsujimura, Yoshiaki Hasegawa, Akihiko Ishibashi, Isao Kidoguchi, Yuzaburo Ban, Masakatsu Suzuki
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Patent number: 6614059Abstract: A semiconductor light-emitting device of Group III-V compound semiconductors includes a quantum well layer, which is formed over a substrate and includes a barrier layer and a well layer that are alternately stacked one upon the other. The band gap of the well layer is narrower than that of the barrier layer. The well layer contains indium and nitrogen, while the barrier layer contains aluminum and nitrogen. In this structure, a tensile strain is induced in the barrier layer, and therefore, a compressive strain induced in the quantum well layer can be reduced. As a result, a critical thickness, at which pits are created, can be increased.Type: GrantFiled: January 7, 2000Date of Patent: September 2, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ayumu Tsujimura, Yoshiaki Hasegawa, Akihiko Ishibashi, Isao Kidoguchi, Yuzaburo Ban, Masakatsu Suzuki
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Patent number: 6611005Abstract: The method for producing a semiconductor of the present invention grows a compound semiconductor on a substrate held by a susceptor provided, in a reaction chamber in accordance with a metalorganic vapor phase epitaxy technique. The method includes the steps of: supplying a Group III source gas containing indium and a Group V source gas containing nitrogen into the reaction chamber; and mixing the Group III and Group V source gases, supplied into the reaction chamber, with each other, and supplying a rare gas as a carrier gas into the reaction chamber so as to carry the mixed source gas onto the upper surface of the substrate.Type: GrantFiled: March 2, 2001Date of Patent: August 26, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ayumu Tsujimura, Yoshiaki Hasegawa, Akihiko Ishibashi, Isao Kidoguchi, Yuzaburo Ban
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Publication number: 20030143771Abstract: The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0≦u, v, w≦1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0≦x, y, z≦1 and x+y+z=1, by using, as a seed crystal, C planes corresponding to top faces of the convexes exposed from the mask film.Type: ApplicationFiled: January 16, 2003Publication date: July 31, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Isao Kidoguchi, Akihiko Ishibashi, Ryoko Miyanaga, Gaku Sugahara, Masakatsu Suzuki, Masahiro Kume, Yuzaburo Ban, Kiyoyuki Morita, Ayumu Tsujimura, Yoshiaki Hasegawa