Patents by Inventor Ayush Kulshrestha
Ayush Kulshrestha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12218664Abstract: Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.Type: GrantFiled: October 21, 2020Date of Patent: February 4, 2025Assignee: Arm LimitedInventors: Sriram Thyagarajan, Yew Keong Chong, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Rajiv Kumar Sisodia
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Patent number: 12087357Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.Type: GrantFiled: June 20, 2022Date of Patent: September 10, 2024Assignee: Arm LimitedInventors: Yew Keong Chong, Sriram Thyagarajan, Andy Wangkun Chen, Arjun Singh, Ayush Kulshrestha
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Patent number: 11900995Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.Type: GrantFiled: April 6, 2021Date of Patent: February 13, 2024Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Ayush Kulshrestha, Munish Kumar
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Publication number: 20230410896Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.Type: ApplicationFiled: June 20, 2022Publication date: December 21, 2023Inventors: Yew Keong Chong, Sriram Thyagarajan, Andy Wangkun Chen, Arjun Singh, Ayush Kulshrestha
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Patent number: 11837543Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.Type: GrantFiled: August 28, 2020Date of Patent: December 5, 2023Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
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Patent number: 11514979Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.Type: GrantFiled: March 31, 2021Date of Patent: November 29, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Munish Kumar, Ayush Kulshrestha, Rajiv Kumar Sisodia, Yew Keong Chong, Kumaraswamy Ramanathan, Edward Martin McCombs, Jr.
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Publication number: 20220319586Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.Type: ApplicationFiled: April 6, 2021Publication date: October 6, 2022Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Ayush Kulshrestha, Munish Kumar
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Publication number: 20220319585Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Andy Wangkun Chen, Munish Kumar, Ayush Kulshrestha, Rajiv Kumar Sisodia, Yew Keong Chong, Kumaraswamy Ramanathan, Edward Martin McCombs, JR.
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Patent number: 11443777Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.Type: GrantFiled: September 11, 2020Date of Patent: September 13, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
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Patent number: 11380384Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.Type: GrantFiled: August 28, 2020Date of Patent: July 5, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
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Patent number: 11322197Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.Type: GrantFiled: October 21, 2020Date of Patent: May 3, 2022Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Sriram Thyagarajan, Yew Keong Chong
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Patent number: 11315628Abstract: Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.Type: GrantFiled: October 21, 2020Date of Patent: April 26, 2022Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony
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Publication number: 20220122654Abstract: Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony
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Publication number: 20220123751Abstract: Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Sriram Thyagarajan, Yew Keong Chong, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Rajiv Kumar Sisodia
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Publication number: 20220122656Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Sriram Thyagarajan, Yew Keong Chong
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Publication number: 20220084561Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.Type: ApplicationFiled: September 11, 2020Publication date: March 17, 2022Inventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony N/A, Ettore Amirante, Ayush Kulshrestha
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Publication number: 20220077857Abstract: Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Inventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
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Patent number: 11271567Abstract: Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.Type: GrantFiled: September 4, 2020Date of Patent: March 8, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
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Publication number: 20220068346Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
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Publication number: 20220068813Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
