Patents by Inventor Ayush Mittal
Ayush Mittal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11736071Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.Type: GrantFiled: March 22, 2021Date of Patent: August 22, 2023Assignee: QUALCOMM IncorporatedInventors: Ayush Mittal, Sreenivasa Mallia, Arpit Gupta, Krishnaswamy Thiagarajan, Bhushan Shanti Asuri
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Publication number: 20220302883Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.Type: ApplicationFiled: March 22, 2021Publication date: September 22, 2022Inventors: Ayush MITTAL, Sreenivasa MALLIA, Arpit GUPTA, Krishnaswamy THIAGARAJAN, Bhushan Shanti ASURI
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Patent number: 10742244Abstract: A device has a first switch in a first transmit path coupled between an output of a first DAC (digital-to-analog converter) in the first transmit path and an input of a first baseband filter in the first transmit path. The device also includes a second switch coupled between the output of the first DAC and an input of a second baseband filter in a second transmit path. The second switch is permanently open. The device also has a third switch and a fourth switch. The third switch is coupled between an output of a second DAC in the second transmit path and the input of the second baseband filter. The fourth switch is coupled between the output of the second DAC and the input of the first baseband filter.Type: GrantFiled: December 3, 2019Date of Patent: August 11, 2020Assignee: QUALCOMM IncorporatedInventors: Ayush Mittal, Arnab Chakraborty, Krishnaswamy Thiagarajan
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Patent number: 10630239Abstract: In certain aspects, an apparatus includes a plurality of phase generators configured to generate a first plurality of local oscillator (LO) phase signals, wherein the plurality of phase generators includes a first set of phase generators and a second set of phase generators. The apparatus also includes a duty cycle generator coupled to the plurality of phase generators, wherein the duty cycle generator is configured to receive the first plurality of LO phase signals and to generate a second plurality of LO phase signals by converting a duty cycle of each of the first plurality of LO phase signals. The first set of phase generators is located adjacent to a first side of the duty cycle generator and the second set of phase generators is located adjacent to a second side of the duty cycle generator, the second side being opposite the first side.Type: GrantFiled: June 12, 2019Date of Patent: April 21, 2020Assignee: QUALCOMM IncorporatedInventors: Ayush Mittal, Gajanan Maroti Devpuje, Krishnaswamy Thiagarajan, Bhushan Shanti Asuri
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Patent number: 10454509Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.Type: GrantFiled: April 25, 2018Date of Patent: October 22, 2019Assignee: QUALCOMM IncorporatedInventors: Bhushan Shanti Asuri, Krishnaswamy Thiagarajan, Ashok Swaminathan, Shahin Mehdizad Taleie, Yen-Wei Chang, Vinod Panikkath, Sameer Vasantlal Vora, Ayush Mittal, Tonmoy Biswas, Sy-Chyuan Hwu, Zhilong Tang, Ibrahim Chamas, Ping Wing Lai, Behnam Sedighi, Dongwon Seo, Nitz Saputra
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Patent number: 10447280Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.Type: GrantFiled: September 21, 2017Date of Patent: October 15, 2019Assignee: QUALCOMM IncorporatedInventors: Ayush Mittal, Gajanan Maroti Devpuje, Bhushan Shanti Asuri, Krishnaswamy Thiagarajan
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Publication number: 20190288722Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.Type: ApplicationFiled: April 25, 2018Publication date: September 19, 2019Inventors: Bhushan Shanti ASURI, Krishnaswamy THIAGARAJAN, Ashok SWAMINATHAN, Shahin MEHDIZAD TALEIE, Yen-Wei CHANG, Vinod PANIKKATH, Sameer Vasantlal VORA, Ayush MITTAL, Tonmoy BISWAS, Sy-Chyuan HWU, Zhilong TANG, Ibrahim CHAMAS, Ping Wing LAI, Behnam SEDIGHI, Dongwon SEO, Nitz SAPUTRA
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Patent number: 10348528Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.Type: GrantFiled: March 29, 2017Date of Patent: July 9, 2019Assignee: QUALCOMM IncorporationInventors: Ayush Mittal, Bhushan Shanti Asuri, Krishnaswamy Thiagarajan, Sameer Vasantlal Vora, Mahim Ranjan
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Patent number: 10348246Abstract: An apparatus is disclosed for mixer biasing with baseband filter common-mode voltage. In an example aspect, the apparatus includes a mixer, a baseband filter, and a bias circuit. The mixer has a mixer transistor that is coupled to a bias node and a baseband node. The baseband filter is coupled to the mixer via the baseband node. The baseband filter is configured to operate with a common-mode reference voltage that is associated with a common-mode voltage applied at the baseband node. The bias circuit is coupled to the baseband filter and the bias node. The bias circuit is configured to receive the common-mode reference voltage from the baseband filter and generate, at the bias node, a bias voltage for biasing the mixer transistor based on the common-mode reference voltage.Type: GrantFiled: January 4, 2018Date of Patent: July 9, 2019Assignee: QUALCOMM IncorporatedInventors: Ayush Mittal, Krishnaswamy Thiagarajan, Bhushan Shanti Asuri, Mahim Ranjan
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Publication number: 20190207558Abstract: An apparatus is disclosed for mixer biasing with baseband filter common-mode voltage. In an example aspect, the apparatus includes a mixer, a baseband filter, and a bias circuit. The mixer has a mixer transistor that is coupled to a bias node and a baseband node. The baseband filter is coupled to the mixer via the baseband node. The baseband filter is configured to operate with a common-mode reference voltage that is associated with a common-mode voltage applied at the baseband node. The bias circuit is coupled to the baseband filter and the bias node. The bias circuit is configured to receive the common-mode reference voltage from the baseband filter and generate, at the bias node, a bias voltage for biasing the mixer transistor based on the common-mode reference voltage.Type: ApplicationFiled: January 4, 2018Publication date: July 4, 2019Inventors: Ayush MITTAL, Krishnaswamy THIAGARAJAN, Bhushan Shanti ASURI, Mahim RANJAN
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Publication number: 20190089358Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.Type: ApplicationFiled: September 21, 2017Publication date: March 21, 2019Inventors: Ayush Mittal, Gajanan Maroti Devpuje, Bhushan Shanti Asuri, Krishnaswamy Thiagarajan
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Patent number: 10164637Abstract: A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit for shifting a first logic domain to a second logic domain. In particular, the level shifting circuit can receive an input signal having a first logic domain with a first high voltage and a first low voltage. The level shifting circuit can receive inputs corresponding to a second high voltage and a second low voltage from the second logic domain. The level shifting circuit can concurrently switch the first high voltage and first low voltage at the input to the second high voltage and the second low voltage to produce a level-shifted version of the input signal at the output. The level shifting circuit can also have a plurality of guard transistors that prevent overvoltage of the circuit components.Type: GrantFiled: February 24, 2017Date of Patent: December 25, 2018Assignee: QUALCOMM IncorporatedInventors: Sreenivasa Mallia, Ayush Mittal, Krishnaswamy Thiagarajan, Karthikeya Aruppukottai Boominathan
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Publication number: 20180248551Abstract: A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit for shifting a first logic domain to a second logic domain. In particular, the level shifting circuit can receive an input signal having a first logic domain with a first high voltage and a first low voltage. The level shifting circuit can receive inputs corresponding to a second high voltage and a second low voltage from the second logic domain. The level shifting circuit can concurrently switch the first high voltage and first low voltage at the input to the second high voltage and the second low voltage to produce a level-shifted version of the input signal at the output. The level shifting circuit can also have a plurality of guard transistors that prevent overvoltage of the circuit components.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Inventors: Sreenivasa MALLIA, Ayush MITTAL, Krishnaswamy THIAGARAJAN, Karthikeya ARUPPUKOTTAI BOOMINATHAN
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Publication number: 20180139078Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.Type: ApplicationFiled: March 29, 2017Publication date: May 17, 2018Inventors: Ayush Mittal, Bhushan Shanti Asuri, Krishnaswamy Thiagarajan, Sameer Vasantlal Vora, Mahim Ranjan
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Patent number: 9660585Abstract: A class AB amplifier may include an input stage, a first folded cascode stage, a second folded cascode stage, and a class AB output stage. In some embodiments, the class AB output stage may provide differential output signals. The common-mode voltage of the differential output signals may be controlled via a correction signal coupled to a selected folded cascode stage. The correction signal may control the common-mode voltage of the differential output signals by altering bias currents within the selected folded cascode stage. The other cascode stage may include bias currents controlled by relatively fixed bias voltages.Type: GrantFiled: June 17, 2015Date of Patent: May 23, 2017Assignee: QUALCOMM IncorporatedInventors: Ayush Mittal, Gireesh Rajendran, Rahul Karmaker
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Publication number: 20160373062Abstract: A class AB amplifier may include an input stage, a first folded cascode stage, a second folded cascode stage, and a class AB output stage. In some embodiments, the class AB output stage may provide differential output signals. The common-mode voltage of the differential output signals may be controlled via a correction signal coupled to a selected folded cascode stage. The correction signal may control the common-mode voltage of the differential output signals by altering bias currents within the selected folded cascode stage. The other cascode stage may include bias currents controlled by relatively fixed bias voltages.Type: ApplicationFiled: June 17, 2015Publication date: December 22, 2016Inventors: Ayush Mittal, Gireesh Rajendran, Rahul Karmaker
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Patent number: 9160309Abstract: An area efficient baseband filter is disclosed. In an exemplary embodiment, an apparatus includes a current to voltage (I-V) filter configured to receive an input current signal at an input port and generate a filtered output voltage signal at an output port based on a feedback transconductance. The input current signal comprises an input DC current in addition to a signal current. The apparatus also includes a feedback circuit connected between the output port and the input port, the feedback circuit having at least one transistor configured to couple the input DC current to a signal ground and to provide the feedback transconductance for the I-V filter.Type: GrantFiled: December 11, 2013Date of Patent: October 13, 2015Assignee: Qualcomm IncorporatedInventors: Gireesh Rajendran, Rakesh Kumar, Vinod Venugopal Panikkath, Ayush Mittal, Alok Joshi
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Publication number: 20150162895Abstract: An area efficient baseband filter is disclosed. In an exemplary embodiment, an apparatus includes a current to voltage (I-V) filter configured to receive an input current signal at an input port and generate a filtered output voltage signal at an output port based on a feedback transconductance. The input current signal comprises an input DC current in addition to a signal current. The apparatus also includes a feedback circuit connected between the output port and the input port, the feedback circuit having at least one transistor configured to couple the input DC current to a signal ground and to provide the feedback transconductance for the I-V filter.Type: ApplicationFiled: December 11, 2013Publication date: June 11, 2015Applicant: QUALCOMM IncorporatedInventors: Gireesh Rajendran, Rakesh Kumar, Vinod Venugopal Panikkath, Ayush Mittal, Alok Joshi