Abstract: A technique for decoding low-density parity check codes includes performing a combined check node and variable node calculation. Decoding is initialized using channel likelihood values estimated from a received physical signal. The decoding iteratively updates the variable nodes. Performing a combined check node and variable node calculation can enable reduced memory usage and faster convergence for the decoder.

Abstract: A source controller provides a block of n×a information bits as n separate rows each with a information bits. A row encoder has an input coupled to an output of the source controller and includes a plurality of accumulators arranged to process m of the information bits in one clock cycle to generate row forward error correction FEC bits. At least one column encoder has an input coupled to an output of the source controller and is arranged to generate column FEC bits in parallel with the row encoder. A multiplexer is coupled to outputs of the row and column encoders and is adapted to serially output an nth row of information bits followed by the nth row FEC bits for each of the n rows, followed by additional rows of FEC bits generated by the column encoder. The terms n, m, and a are integers greater than one. Where more than one column encoder is used, there are preferably m column encoders in parallel and each operating at one bit per clock cycle.

Abstract: A system and method for parallel Pseudo-random Noise (PN) code generation is disclosed. The method includes the operation of producing a PN code sequence having a predetermined length. The PN code can be divided into L segments. At least one of the L segments can have a length less than other segments. The L segments can be distributed into an array of L digital memories. Each of the digital memories can output every Lth chip of the PN code in parallel at a selected rate. An element of the PN code can be substituted from an element substitution cache into the output of the L digital memories to compensate for segment(s) having a shorter length.

Abstract: Method and apparatus are disclosed for obtaining improved performance when using Forward Error Correction (FEC) with channels experiencing block fading or burst jamming over some number of contiguous symbols. One suitable application is when the channel is periodically obstructed due to the rotation of a propeller blade, resulting in a periodic block fading channel. During operation zero symbols are inserted into the received signal stream, prior to the FEC decoder at times that are estimated or otherwise determined to correspond to periods of jamming or severe fading. The zero symbols effectively “erase” the severely degraded symbols. The zero symbols are less detrimental to the FEC decoder than the severely degraded symbols, especially when the channel interleaving/de-interleaving operations result in the zero symbols being temporarily distributed over a large block of received symbols.

Abstract: A technique for resolving access contention in a parallel turbo decoder is described. The technique includes associating a plurality of buffer memories with the subdecoders so that accesses to banks of a shared interleaver memory can be rescheduled. Accesses can be rescheduled to prevent simultaneous accesses to a single bank of the shared interleaver memory based on an interleaver pattern.

Abstract: The invention provides a system and method for generating a high rate pseudo-random noise (PN) code with a parallel PN generator. The method includes the operation of configuring L programmable PN generators to each output every Lth chip of a PN code. Select PN generators of the L PN generators can be configured to have their output delayed for a predetermined number of chips less than or equal to L when a fine slip is needed to allow the high rate PN code to be delayed for a set number of chips to synchronize the high rate PN code with another PN code. The outputs of each of the L programmable PN generators can be multiplexed to produce the high rate PN code.