Abstract: A permutation apparatus can receive a data block of ordered data elements in parallel data segments that are Pin number of data elements wide. The permutation apparatus can perform a parallel-to-parallel conversion and one or more reorder operations on the data elements and output the data block in parallel data segments that are Pout number of data elements wide and in which at least some of the data elements are reordered. The Pin-parallel-data segments can be clocked into the permutation apparatus on successive cycles of a clock, and the Pout-parallel-data segments can be clocked out of the permutation apparatus on cycles of the same clock.

Abstract: A decoder for decoding received vectors r encoded in accordance with a forward error correction code having a parity check matrix H with multiple regions at least two of which have patterns of ones with different pattern characteristics. The decoder can include a permuted decode module configured to decode in accordance with a permuted version of the parity check matrix H in which the ones in one of the regions are permuted into a permuted pattern that has a pattern characteristic of the other region. The decoder can also include a reorder module that permutes probabilities of a received vector r to be decoded to correspond with the permuted parity check matrix H.

Abstract: A symbol de-mapper can determine soft values for the bits of a complex symbol R that has been transmitted and received at a receiving device. The symbol de-mapper can reduce the number of calculations needed to determine soft values of the bits by limiting the symbols S utilized to calculate the soft values to subsets of the symbols S associated with sectors of symbol rings in the symbol constellation.

Abstract: A method of branch metric calculation of trellis coded data, suitable for a decoder of phase angle on a carrier modulated with phase shift keying (PSK) modulation, begins with an expressing angles of phase shift by a vectorial representation of sectors within quadrants of a circle. The sectors are subdivided into sub-sectors of differing sizes, and the sub-sectors are divided further into equal increments of angle referred to as PIEs. The PIEs and the quadrants are identified and, in each quadrant, there is an assigning of a set of branch metrics to serve as identifiers of respective ones of the sub-sectors in each sector of the quadrant. The set of branch metrics in one sector of the quadrant differs from the set of branch metrics in another of the sectors of the quadrant by a permutation of the branch metrics. The phase data is outputted in the form of branch metrics and quadrant for use by a decoder such as a Viterbi decoder.

Abstract: A system including coding and decoding circuits provides for resolution of the phase ambiguities in pragmatic trellis-coded PSK modulation transmissions. An error correcting coder, such as a convolutional encoder, precedes the modulator for reducing the effect of noise in inducing phase errors. A corresponding decoder appears at the reception end of the communication system. A differential encoder and decoder automatically remove the possible phase ambiguities, and operate in conjunction with the error correcting encoder and decoder. Each of the ambiguity-removal differential encoder and the decoder act as an operator upon its input signal. In order that both the error correcting encoder and the ambiguity encoder immediately precede the modulator, the ambiguity removal circuitry is placed between the error correcting encoder, and is constructed as a combination of differential encoder and inverse differential encoder.

Abstract: A novel maximum likeihood decoder for the Golay (24,12) code is provided. Instead of decoding the received dimensional vector (X) is a systolic array, the vector is mapped into a (24,5) subcode with an index 128 which is easily decoded. The decoder employs a plurality of precomputational circuits cooperating with a similar plurality of inner product circuits which compute the 128 inner product values and select the maximum inner product value from each inner product circuit. The maximum inner product value from each circuit is loaded into a select logic circuit for selecting the maximum inner product value and its corresponding code word closest to the received vector (X).