Abstract: An anti-ferromagnetic (AFM) voltage-controlled field effect logic device structure can include an AFM material that extends in a first direction and an input voltage terminal that extends opposite the AFM material. An oxide material can be located between the AFM material and the input voltage terminal. A first spin orbital coupling (SOC) material can extend in a second direction across the AFM material to provide a first SOC channel with a drain voltage terminal at a first end of the first SOC channel and an output voltage terminal at a second end of the first SOC channel that is opposite the first end. A contact can be electrically coupled to the output voltage terminal and configured to electrically couple to a second SOC material extending in the second direction spaced apart from the first SOC material to provide a second SOC channel.

Abstract: A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over ? with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.

Abstract: An anti-ferromagnetic (AFM) voltage-controlled field effect logic device structure can include an AFM material that extends in a first direction and an input voltage terminal that extends opposite the AFM material. An oxide material can be located between the AFM material and the input voltage terminal. A first spin orbital coupling (SOC) material can extend in a second direction across the AFM material to provide a first SOC channel with a drain voltage terminal at a first end of the first SOC channel and an output voltage terminal at a second end of the first SOC channel that is opposite the first end. A contact can be electrically coupled to the output voltage terminal and configured to electrically couple to a second SOC material extending in the second direction spaced apart from the first SOC material to provide a second SOC channel.

Abstract: A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over ? with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.

Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.

Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.

Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.

Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.

Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition.

Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition.

Abstract: Ultra-low power single metallic single-wall-nano-tube (SWNT) interconnects for sub-threshold circuits are provided. According to some embodiments, an interconnect structure for use in electronic circuits can generally comprise a first substrate, a second substrate, and an interconnect. The first substrate can be spaced apart from the second substrate. The interconnect is preferably a single wall carbon nanotube (SWNT) interconnect. The SWNT interconnect can be disposed between the first and second substrates to electrically connect the substrates. The substrates can form parts of electrical components (e.g., a transistor, processor, memory, filters, etc.) operating in a subthreshold operational state. Other aspects, features, and embodiments are claimed and described.