Patents by Inventor Azad Nassor

Azad Nassor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6687800
    Abstract: The invention relates to a chip card (21) including an information processing means and main information storage means, which operates to load and unload a programmable memory as a function of the need for the program run by the card and for applicative data. The processing means comprises a means for detecting, during the operation of the chip card, that the main storage means contain a quantity of information such that the execution of an operation is not possible. The chip card also includes a means for selecting, in the main storage means, a set of information (K) to be unloaded. The unloading of the set of information (K) releases enough space in the main storage means to allow the execution of the operation. Also included is a means for unloading the set of information (K) to be unloaded into secondary storage means (23 through 25), in the event that the secondary storage means does not contain the set of information to be unloaded.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: February 3, 2004
    Assignee: Bull CP8
    Inventor: Azad Nassor
  • Patent number: 6536034
    Abstract: The present invention relates to a process and a device for modifying code sequences written into a first memory (2) of a medium. A central processing unit (1) executes code sequences and the first memory contains a main program comprising at least one code sequence executable by the central processing unit (1). The first memory also comprises a second, programmable nonvolatile memory (3), and a third working memory (4). A branch table TAB_DER contained in the second programmable memory contains at least one field containing reference data for a new code sequence stored in one of the memories. Branching instructions allow a deferred branch from the executed code sequence to the new code sequence written into one of the three memories. Instructions in the new code sequence allow the return to a point of the code sequence executed before the branch.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: March 18, 2003
    Assignee: Bull CP8
    Inventor: Azad Nassor