Patents by Inventor Azeez Jennudin Bhavnagarwala

Azeez Jennudin Bhavnagarwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, system and device for non-volatile memory device operation
    Patent number: 10431304
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: October 1, 2019
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Vivek Asthana, Piyush Agarwal, Akshay Kumar, Lucian Shifren
  • Circuit and method for configurable impedance array
    Patent number: 10381076
    Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 13, 2019
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Vikas Chandra, Brian Tracy Cline
  • Selective writes in a storage element
    Patent number: 10181350
    Abstract: A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 15, 2019
    Assignee: Arm Limited
    Inventors: Shidhartha Das, Andreas Hansson, Akshay Kumar, Piyush Agarwal, Azeez Jennudin Bhavnagarwala, Lucian Shifren
  • Method, system and device for non-volatile memory device operation
    Patent number: 10127981
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 13, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION
    Publication number: 20180254084
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Application
    Filed: April 30, 2018
    Publication date: September 6, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION
    Publication number: 20180247693
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.
    Type: Application
    Filed: March 26, 2018
    Publication date: August 30, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Vivek Asthana, Piyush Agarwal, Akshay Kumar, Lucian Shifren
  • Method, system and device for non-volatile memory device operation
    Patent number: 10062435
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 28, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Piyush Agarwal, Akshay Kumar
  • CIRCUIT AND METHOD FOR CONFIGURABLE IMPEDANCE ARRAY
    Publication number: 20180218772
    Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.
    Type: Application
    Filed: January 8, 2018
    Publication date: August 2, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Vikas Chandra, Brian Tracy Cline
  • Method, system and device for non-volatile memory device operation
    Patent number: 9990992
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: June 5, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • Method, system and device for power-up operation
    Patent number: 9972388
    Abstract: Disclosed are methods, systems and devices for powering up devices including non-volatile memory elements in an array of non-volatile memory elements. In one aspect, during a sequence for powering up an integrated device, non-volatile memory elements may be isolated from voltage supplies to avoid in advertent changes of memory states stored in the non-volatile memory elements.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: May 15, 2018
    Assignee: ARM Ltd.
    Inventors: Shidhartha Das, Piyush Agarwal, Akshay Kumar, Azeez Jennudin Bhavnagarwala
  • METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION
    Publication number: 20180122463
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.
    Type: Application
    Filed: September 21, 2017
    Publication date: May 3, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Piyush Agarwal, Akshay Kumar
  • METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION
    Publication number: 20180114574
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Application
    Filed: October 25, 2016
    Publication date: April 26, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • SELECTIVE WRITES IN A STORAGE ELEMENT
    Publication number: 20180114575
    Abstract: A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.
    Type: Application
    Filed: December 14, 2017
    Publication date: April 26, 2018
    Applicant: ARM Limited
    Inventors: Shidhartha DAS, Andreas HANSSON, Akshay KUMAR, Piyush AGARWAL, Azeez Jennudin BHAVNAGARWALA, Lucian SHIFREN
  • Method, system and device for non-volatile memory device operation
    Patent number: 9947402
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: April 17, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Vivek Asthana, Piyush Agarwal, Akshay Kumar, Lucian Shifren
  • METHOD, SYSTEM AND DEVICE FOR POWER-UP OPERATION
    Publication number: 20180102170
    Abstract: Disclosed are methods, systems and devices for powering up devices including non-volatile memory elements in an array of non-volatile memory elements. In one aspect, during a sequence for powering up an integrated device, non-volatile memory elements may be isolated from voltage supplies to avoid in advertent changes of memory states stored in the non-volatile memory elements.
    Type: Application
    Filed: October 12, 2016
    Publication date: April 12, 2018
    Inventors: Shidhartha Das, Piyush Agarwal, Akshay Kumar, Azeez Jennudin Bhavnagarwala
  • Circuit and method for configurable impedance array
    Patent number: 9905295
    Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 27, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Vikas Chandra, Brian Tracy Cline
  • Selective writes in a storage element
    Patent number: 9859003
    Abstract: A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: January 2, 2018
    Assignee: ARM Limited
    Inventors: Shidhartha Das, Andreas Hansson, Akshay Kumar, Piyush Agarwal, Azeez Jennudin Bhavnagarwala, Lucian Shifren
  • Method, system and device for non-volatile memory device operation
    Patent number: 9792984
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: October 17, 2017
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Piyush Agarwal, Akshay Kumar
  • Circuit and method for configurable impedance array
    Patent number: 9773550
    Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 26, 2017
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Vikas Chandra, Brian Tracy Cline
  • CIRCUIT AND METHOD FOR CONFIGURABLE IMPEDANCE ARRAY
    Publication number: 20170206963
    Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.
    Type: Application
    Filed: March 8, 2017
    Publication date: July 20, 2017
    Inventors: Azeez Jennudin Bhavnagarwala, Vikas Chandra, Brian Tracy Cline