Patents by Inventor Azuma Araya

Azuma Araya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10008919
    Abstract: A method of controlling a power supply to a semiconductor device including a first region having a high-side drive circuit, a second region having a signal processing circuit, a low-side drive circuit and a voltage control circuit, and a separation region formed between the first and second regions and having a rectifying element, includes turning on a first control signal to the voltage control circuit, turning off the first control signal to the voltage control circuit, and repeating the turning on of the first control signal and the turning off the first control signal.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 26, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Kaya, Yasushi Nakahara, Azuma Araya, Ryo Kanda, Tomonobu Kurihara, Tetsu Toda
  • Publication number: 20160164398
    Abstract: A method of controlling a power supply to a semiconductor device including a first region having a high-side drive circuit, a second region having a signal processing circuit, a low-side drive circuit and a voltage control circuit, and a separation region formed between the first and second regions and having a rectifying element, includes turning on a first control signal to the voltage control circuit, turning off the first control signal to the voltage control circuit, and repeating the turning on of the first control signal and the turning off the first control signal.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 9, 2016
    Inventors: Yoshinori Kaya, Yasushi Nakahara, Azuma Araya, Ryo Kanda, Tomonobu Kurihara, Tetsu Toda
  • Patent number: 9287256
    Abstract: Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: March 15, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Kaya, Yasushi Nakahara, Azuma Araya, Ryo Kanda, Tomonobu Kurihara, Tetsu Toda
  • Publication number: 20150115342
    Abstract: Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 30, 2015
    Inventors: Yoshinori KAYA, Yasushi NAKAHARA, Azuma ARAYA, Ryo KANDA, Tomonobu KURIHARA, Tetsu TODA
  • Patent number: 8659145
    Abstract: A semiconductor device in which a flip chip is mounted which can change a potential of a specific terminal without changing a design of a package external. The semiconductor device includes an IC chip having a bump for an external terminal, and a package in which the IC chip is mounted. The package includes an inner lead portion that supplies a first signal or a second signal to the external terminal. The inner lead portion has a pattern of an inner lead that can change a signal to be supplied to the external terminal to the first signal or the second signal according to a position at which the IC chip is mounted.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: February 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Azuma Araya
  • Publication number: 20130069212
    Abstract: A semiconductor device in which a flip chip is mounted which can change a potential of a specific terminal without changing a design of a package external. The semiconductor device includes an IC chip having a bump for an external terminal, and a package in which the IC chip is mounted. The package includes an inner lead portion that supplies a first signal or a second signal to the external terminal. The inner lead portion has a pattern of an inner lead that can change a signal to be supplied to the external terminal to the first signal or the second signal according to a position at which the IC chip is mounted.
    Type: Application
    Filed: July 27, 2012
    Publication date: March 21, 2013
    Inventor: Azuma ARAYA
  • Patent number: 7506183
    Abstract: Suppression malfunction of an authentication circuit for authenticating a battery pack. Signal line for applying an intermediate potential between the power supply and ground and for reading the potential of a thermistor for detecting the temperature is used as a transmission path for exchanging data between a battery pack and main device. A master-authentication circuit and slave-authentication circuit comprise level-correction circuits, which are connected to the signal line by way of a voltage-comparator circuit. The level-correction circuits are constructed such that they correct the signal applied to the signal line so that it is greater than or less than the unstable-region voltage, and outputs it to the input end of the authentication circuits, so that unstable-region voltage is not applied to the input end.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: March 17, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Azuma Araya
  • Publication number: 20090033645
    Abstract: A display device includes: a display control circuit and a memory. The display control circuit drives a display panel. The memory stores setting data for the display panel. The display control circuit reads the setting data from the memory in response to a blanking start signal indicative of a start timing of a blanking interval.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 5, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Azuma Araya
  • Publication number: 20060108972
    Abstract: Suppression malfunction of an authentication circuit for authenticating a battery pack. Signal line for applying an intermediate potential between the power supply and ground and for reading the potential of a thermistor for detecting the temperature is used as a transmission path for exchanging data between a battery pack and main device. A master-authentication circuit and slave-authentication circuit comprise level-correction circuits, which are connected to the signal line by way of a voltage-comparator circuit. The level-correction circuits are constructed such that they correct the signal applied to the signal line so that it is greater than or less than the unstable-region voltage, and outputs it to the input end of the authentication circuits, so that unstable-region voltage is not applied to the input end.
    Type: Application
    Filed: November 22, 2005
    Publication date: May 25, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Azuma Araya