Patents by Inventor B. Chen

B. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250094395
    Abstract: An integrated platform system that employ a series of machine learning techniques and prediction and detection units that can process input data and extract and generate meaningful insights and predictions therefrom. The system integrates together multiple different data storage types and applications that generates data of different types, and an associated processing system for processing the different data types, store the data in a common data model to normalize the data, determine the data lineage of the data, and then process the data using different types of techniques. The data can also be processed by a prediction unit for generating meaningful insights and predictions or by an anomaly detection unit for detecting one or more anomalies in the data.
    Type: Application
    Filed: June 24, 2024
    Publication date: March 20, 2025
    Inventors: Niels HANSON, James Johnson GARDNER, Punit S. ORPE, Wendy DU, Laurence Anthony BROWN, Ranjan Vivek MANNIGE, David GREEN, Michael AHN, Yang ZHOU, Andrew YUAN, Adam Helio ROSA, Kyle B. CHEN, Alex PERUSSE, Christian Alexander MANAOG, Yeshwanth SOMU, Xin CHENG, Torey C. BEARLY, Raghav SABOO, Sphoorthy PAMARAJU, Erik ERNST, Can OZURETMEN, Yuan ZHANG
  • Patent number: 12019596
    Abstract: An integrated platform system that employ a series of machine learning techniques and prediction and detection units that can process input data and extract and generate meaningful insights and predictions therefrom. The system integrates together multiple different data storage types and applications that generates data of different types, and an associated processing system for processing the different data types, store the data in a common data model to normalize the data, determine the data lineage of the data, and then process the data using different types of techniques. The data can also be processed by a prediction unit for generating meaningful insights and predictions or by an anomaly detection unit for detecting one or more anomalies in the data.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: June 25, 2024
    Assignee: KPMG LLP
    Inventors: Niels Hanson, James Johnson Gardner, Punit S. Orpe, Wendy Du, Laurence Anthony Brown, Ranjan Vivek Mannige, David Green, Michael Ahn, Yang Zhou, Andrew Yuan, Adam Helio Rosa, Kyle B. Chen, Alex Perusse, Christian Alexander Manaog, Yeshwanth Somu, Xin Cheng, Torey C. Bearly, Raghav Saboo, Sphoorthy Pamaraju, Erik Ernst, Can Ozuretmen, Yuan Zhang
  • Publication number: 20230369444
    Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Albert B. Chen, Mark Armstrong, Afrin Sultana, Van H. Le, Travis W. Lajoie, Shailesh Kumar Madisetti, Timothy Jen, Cheng Tan, Moshe Dolejsi, Vishak Venkatraman, Christopher Ryder, Deepyanti Taneja
  • Publication number: 20230369426
    Abstract: Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Travis W. Lajoie, Van H. Le, Timothy Jen, Kamal H. Baloch, Mark Armstrong, Albert B. Chen, Moshe Dolejsi, Shailesh Kumar Madisetti, Afrin Sultana, Deepyanti Taneja, Vishak Venkatraman
  • Publication number: 20230369503
    Abstract: Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Cheng Tan, Van H. Le, Akash Garg, Shokir A. Pardaev, Timothy Jen, Abhishek Anil Sharma, Thiruselvam Ponnusamy, Moira C. Vyner, Caleb Barrett, Forough Mahmoudabadi, Albert B. Chen, Travis W. Lajoie, Christopher M. Pelto
  • Publication number: 20230371233
    Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Travis W. Lajoie, Forough Mahmoudabadi, Shailesh Kumar Madisetti, Van H. Le, Timothy Jen, Cheng Tan, Jisoo Kim, Miriam R. Reshotko, Vishak Venkatraman, Eva Vo, Yue Zhong, Yu-Che Chiu, Moshe Dolejsi, Lorenzo Ferrari, Akash Kannegulla, Deepyanti Taneja, Mark Armstrong, Kamal H. Baloch, Afrin Sultana, Albert B. Chen, Vamsi Evani, Yang Yang, Juan G. Alzate-Vinasco, Fatih Hamzaoglu
  • Publication number: 20230317615
    Abstract: An integrated circuit includes a first layer, and a second layer above the first layer. A third layer is between a first section of the first layer and a first section of the second layer. A fourth layer is laterally adjacent to the third layer, the fourth layer between a second section of the first layer and a second section of the second layer. In an example, a first dielectric material of the third layer is different (e.g., one or both of compositionally different and structurally different) from a second dielectric material of the fourth layer. In an example, the third and fourth layers are etch stop layers. In some cases, the third and fourth layers are coplanar with each other with respect to their top surfaces, or their bottom surfaces, or both their top and bottom surfaces.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Deepyanti Taneja, Travis W. Lajoie, Abhishek Anil Sharma, Gregory J. George, Tarannum Tiasha, Huiying Liu, Yue Liu, Moshe Dolejsi, Vinaykumar V. Hadagali, Shardul Wadekar, Vladimir Nikitin, Albert B. Chen, Daniel J. Schinke, James O'Donnell
  • Publication number: 20230267105
    Abstract: An integrated platform system that employ a series of machine learning techniques and prediction and detection units that can process input data and extract and generate meaningful insights and predictions therefrom. The system integrates together multiple different data storage types and applications that generates data of different types, and an associated processing system for processing the different data types, store the data in a common data model to normalize the data, determine the data lineage of the data, and then process the data using different types of techniques. The data can also be processed by a prediction unit for generating meaningful insights and predictions or by an anomaly detection unit for detecting one or more anomalies in the data.
    Type: Application
    Filed: January 13, 2023
    Publication date: August 24, 2023
    Inventors: Niels Hanson, James Johnson Gardner, Punit S. Orpe, Wendy Du, Laurence Anthony Brown, JR., Ranjan Vivek Mannige, David Green, Michael Ahn, Yang Zhou, Andrew Yuan, Adam Helio Rosa, Kyle B. Chen, Alex Perusse, Christian Alexander Manaog, Yeshwanth Somu, Xin Cheng, Torey C. Bearly, Raghav Saboo, Sphoorthy Pamaraju, Erik Ernst, Can Ozuretmen, Yuan Zhang
  • Publication number: 20230175044
    Abstract: The present description pertains to a detection system and methods of using same comprising an upstream molecular circuitry system that is activated in the presence of a target molecule to produce a reporter molecule and a capture molecule bound to an electrode wherein the reporter molecule specifically binds to the capture molecule bound to the electrode to produce or reduce a detectable electrochemical signal.
    Type: Application
    Filed: October 29, 2020
    Publication date: June 8, 2023
    Inventors: Keith Pardee, Shana O. Kelley, Sarah J. Smith, Peivand S. Mousavi, Jenise B. Chen, Wenhan Liu
  • Publication number: 20230107004
    Abstract: A biosensor comprising an electrode and inverted molecular pendulums (iMPs) is described. Each IMP includes a linker bound to the electrode, and an analyte receptor and a redox reporter both bound to the linker. The redox reporter is reactive at positive potential when the linker presents a net negative charge and reactive at negative potential when the linker presents a net positive charge. Upon application of an electric field, the biosensor is characterized by an iMPs unbound state, where no analyte is bound to the receptor, at which the iMPs are displaced towards the electrode and electron transfer from the iMPs towards the electrode occurs at an unbound electron transfer rate, and an iMPs bound state, where the analyte is bound to the receptor, at which the iMPs are displaced towards the electrode and electron transfer from the iMPs towards the electrode occurs at a bound electron transfer rate.
    Type: Application
    Filed: March 2, 2021
    Publication date: April 6, 2023
    Inventors: Shana KELLEY, Edward SARGENT, Jagotamoy DAS, Surath GOMIS, Jenise B. CHEN, Sharif AHMED, Hanie YOUSEFI, Dingran CHANG, Alam MAHMUD
  • Patent number: 11585307
    Abstract: A vehicle determines a first resistance of a starter motor and a starter cable connected thereto based at least in part on the first voltage of a power source. The vehicle determines a predicted minimum battery voltage based at least in part on the first resistance of the starter motor and the starter cable. The vehicle, in response to the predicted minimum battery voltage satisfying a threshold, enables a vehicle stop-start function, and, in response to the predicted minimum battery voltage failing to satisfy the threshold, disables the vehicle stop-start function.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: February 21, 2023
    Assignee: Ford Global Technologies, LLC
    Inventors: Hanyang B. Chen, Ravi Atluru, Michael J. Irby
  • Patent number: 11556510
    Abstract: An integrated platform system that employ a series of machine learning techniques and prediction and detection units that can process input data and extract and generate meaningful insights and predictions therefrom. The system integrates together multiple different data storage types and applications that generates data of different types, and an associated processing system for processing the different data types, store the data in a common data model to normalize the data, determine the data lineage of the data, and then process the data using different types of techniques. The data can also be processed by a prediction unit for generating meaningful insights and predictions or by an anomaly detection unit for detecting one or more anomalies in the data.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: January 17, 2023
    Assignee: KPMG LLP
    Inventors: Niels Hanson, James Johnson Gardner, Punit S. Orpe, Wendy Du, Laurence Anthony Brown, Ranjan Vivek Mannige, David Green, Michael Ahn, Yang Zhou, Andrew Yuan, Adam Helio Rosa, Kyle B. Chen, Alex Perusse, Christian Alexander Manaog, Yeshwanth Somu, Xin Cheng, Torey C. Bearly, Raghav Saboo, Sphoorthy Pamaraju, Erik Ernst, Can Ozuretmen, Yuan Zhang
  • Patent number: 11554731
    Abstract: An electrical system in a vehicle has a battery is configured to supply electrical current when a driver ignition key is in a Key-Off state. A. A plurality of electrical loads are each configurable to receive the electrical current flowing from the battery during the Key-Off state depending upon predetermined Key-Off-Load (KOL) Modes. A vehicle locator determines a geographic location of the vehicle. A sleep-time database records daily Key-On and Key-Off events according to changes between the Key-On state and the Key-Off state, wherein each Key-Off event is associated with a respective geographic location from the vehicle locator. An analyzer identifies Key-Off events sharing a repetitive time span and a common geographic location. A scheduler activates a timed KOL sequence according to the identified Key-Off events so that repetitive time slots of vehicle usage can be used to reduce battery drain during times when vehicle usage is less likely.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: January 17, 2023
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Hanyang B. Chen, Michael J. Irby
  • Publication number: 20220406782
    Abstract: An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Inventors: Abhishek A. Sharma, Albert B. Chen, Wilfred Gomes, Fatih Hamzaoglu, Travis W. Lajoie, Van H. Le, Alekhya Nimmagadda, Miriam R. Reshotko, Hui Jae Yoo
  • Patent number: 11506719
    Abstract: A monitoring method includes, among other things, within a vehicle, providing a first electrical system with an auxiliary battery, and a second electrical system with a primary battery. The method further includes electrically coupling the first electrical system to the second electrical system, electrically loading the auxiliary battery and the primary battery, and comparing an electrical parameter of the auxiliary battery to a threshold value to assess a state of the auxiliary battery.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 22, 2022
    Assignee: Ford Global Technologies, LLC
    Inventors: Hanyang B. Chen, Michael J. Irby, Matthew Thomas Loiselle, William David Treharne, Mark E. Shields, Josephine S. Lee
  • Patent number: 11501583
    Abstract: Systems and methods for monitoring the health of a vehicle battery are described, in which an example vehicle includes a vehicle battery, one or more vehicle battery sensors, and a processor. The processor is configured to determine a battery health metric of the vehicle battery, wherein the battery health metric is based on a battery service time, a battery state of charge, and a battery temperature. The processor is also configured to perform a battery refresh operation on the vehicle battery responsive to determining that the battery health metric is above a refresh threshold. And the processor is further configured to activate a vehicle alert responsive to determining that the battery health metric is above an end-of-life threshold.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: November 15, 2022
    Assignee: Ford Global Technologies, LLC
    Inventors: Hanyang B. Chen, Michael J. Irby
  • Publication number: 20220324399
    Abstract: An electrical system in a vehicle has a battery is configured to supply electrical current when a driver ignition key is in a Key-Off state. A. A plurality of electrical loads are each configurable to receive the electrical current flowing from the battery during the Key-Off state depending upon predetermined Key-Off-Load (KOL) Modes. A vehicle locator determines a geographic location of the vehicle. A sleep-time database records daily Key-On and Key-Off events according to changes between the Key-On state and the Key-Off state, wherein each Key-Off event is associated with a respective geographic location from the vehicle locator. An analyzer identifies Key-Off events sharing a repetitive time span and a common geographic location. A scheduler activates a timed KOL sequence according to the identified Key-Off events so that repetitive time slots of vehicle usage can be used to reduce battery drain during times when vehicle usage is less likely.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 13, 2022
    Inventors: Hanyang B. Chen, Michael J. Irby
  • Patent number: 11458914
    Abstract: An AC inverter in a vehicle operates using a 24 V input when a vehicle powertrain is in a parked/idling state. A first 12 V battery is connected with a first bus segment. A second 12 V battery is connected with a second bus segment. A switch module selectably interconnects the first and second bus segments. In a nominal 12 V state, the batteries are connected in parallel from the bus segments to ground. In a dual voltage state, the batteries are connected in series so the first bus segment is at 12 V and the second bus segment is at 24 V. A first alternator driven by the powertrain provides a regulated voltage to the second bus segment, wherein the regulated voltage corresponds to 12 V when the switch module is in the nominal state and corresponds to 24 V when the switch module is in the dual voltage state.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: October 4, 2022
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Stuart C. Salter, Zeljko Deljevic, Phillip M. Marine, Daniel J. Martin, William C. Taylor, Hanyang B. Chen
  • Patent number: 11251646
    Abstract: A power system for a vehicle comprises a first power supply network configured to operate at a first voltage. The first power supply network comprises a first alternator, a starter motor, and a battery conductively connected to the first alternator and the starter motor. The system further comprises a second power supply network configured to operate at a second voltage. The second power supply network comprises a second alternator, a power supply receptacle configured to output power to an external accessory, and a capacitive energy storage device conductively connected to the second alternator and the power supply receptacle. A directional conduction device interconnects the first power supply network and the second power supply network.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: February 15, 2022
    Assignee: Ford Global Technologies, LLC
    Inventors: Hanyang B. Chen, Michael Irby, Jason Baker, Gabriel Jim, Anthony Thomas Spoto
  • Publication number: 20220040255
    Abstract: The present invention provides methods for remodeling gut microbiome to a desired state. The invention also provides in vitro screening platform for identifying novel agents that can remodel dysfunctional gut microbiome.
    Type: Application
    Filed: September 26, 2019
    Publication date: February 10, 2022
    Inventors: Reza M. Ghadiri, Luke J. Leman, Poshen B. Chen, Yannan Zhao, Ali Torkamani, Audrey Black