Patents by Inventor B. Joshua Rosen

B. Joshua Rosen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250141812
    Abstract: A distributed computing system, such as may be used to implement an electronic trading system, supports a notion of fairness in latency. The system does not favor any particular client. Thus, being connected to a particular access point into the system (such as via a gateway) does not give any particular device an unfair advantage or disadvantage over another. That end is accomplished by precisely controlling latency, that is, the time between when request messages arrive at the system and a time at which corresponding response messages are permitted to leave. The precisely controlled, deterministic latency can be fixed over time, or it can vary according to some predetermined pattern, or vary randomly within a pre-determined range of values.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 1, 2025
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen, Christophe Juhasz
  • Patent number: 12231347
    Abstract: A distributed computing system, such as may be used to implement an electronic trading system, supports a notion of fairness in latency. The system does not favor any particular client. Thus, being connected to a particular access point into the system (such as via a gateway) does not give any particular device an unfair advantage or disadvantage over another. That end is accomplished by precisely controlling latency, that is, the time between when request messages arrive at the system and a time at which corresponding response messages are permitted to leave. The precisely controlled, deterministic latency can be fixed over time, or it can vary according to some predetermined pattern, or vary randomly within a pre-determined range of values.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: February 18, 2025
    Assignee: HYANNIS PORT RESEARCH, INC.
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen, Christophe Juhasz
  • Publication number: 20250047415
    Abstract: Systems and methods are disclosed herein that provide low latency data communication with improved physical link layer reliability through repeated physical layer retransmission of data over a data connection whenever the connection is idle (i.e., no new data to send). In some embodiments, the transmission of administrative control symbols (e.g., “idles,” “commas”, etc.) can be suppressed or otherwise reduced to allow some of the available connection bandwidth to be used for data redundancy and fault tolerance through the repeated retransmission of data as described in more detail below. Accordingly, instead of executing time-consuming error correcting routines, a receive node can discard the erroneous data frame and process at least one repeat frame that carries the same data payload. Sequence numbers and/or other repeat indicators can be used to distinguish original frames from repeat frames and/or for identifying which frames carry the same data payload.
    Type: Application
    Filed: August 28, 2024
    Publication date: February 6, 2025
    Inventors: Anthony D. AMICANGIOLI, B. Joshua ROSEN
  • Patent number: 12107682
    Abstract: Systems and methods are disclosed herein that provide low latency data communication with improved physical link layer reliability through repeated physical layer retransmission of data over a data connection whenever the connection is idle (i.e., no new data to send). In some embodiments, the transmission of administrative control symbols (e.g. “idles,” “commas”, etc.) can be suppressed or otherwise reduced to allow some of the available connection bandwidth to be used for data redundancy and fault tolerance through the repeated retransmission of data as described in more detail below. Accordingly, instead of executing time-consuming error correcting routines, a receive node can discard the erroneous data frame and process at least one repeat frame that carries the same data payload. Sequence numbers and/or other repeat indicators can be used to distinguish original frames from repeat frames and/or for identifying which frames carry the same data payload.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 1, 2024
    Assignee: Hyannis Port Research, Inc.
    Inventors: Anthony D. Amicangioli, B. Joshua Rosen
  • Publication number: 20240192854
    Abstract: A hardware-based electronic trading system is disclosed that minimizes external memory accesses, thereby reducing overall latency. Order data for all open orders of a particular symbol, side, and price may be organized into a defined data structure, or tile, that can be fetched from an external memory cache. Once loaded into an internal memory cache of an FPGA or other fixed logic, the tile may be accessed often with minimal delay to obtain order data for multiple open orders having the same symbol, side, and price. To further minimize the number of external memory accesses, external memory can be provisioned as an asymmetric, multi-level memory cache that is tailored for handling large data sets of matching engine books and ticker plant services. In particular, the multi-level memory cache can be implemented using external memory units in the form of DRAMs for storing tiles according to a price priority scheme.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 13, 2024
    Inventors: Anthony D. AMICANGIOLI, B. Joshua ROSEN, Ryan P. WALSH, Nicola AGUILAR-THOMSON
  • Publication number: 20240193686
    Abstract: Systems and methods are provided herein for efficient data relocation within a multi-level memory cache. In particular, the method can include (i) storing specific data structures, or tiles, in a first memory cache that contain open order data representing open orders for one of buying or selling a financial instrument at consecutive price levels that fall within a defined price range between a most aggressive price and a least aggressive price; (ii) storing multiple tiles in a second memory cache that contain open order data representing open orders for one of buying or selling the financial instrument at prices that fall outside the defined price range; and relocating tiles between the first memory cache and the second memory cache in response to changes in the open order data for one of buying or selling the financial instrument at the most aggressive price.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 13, 2024
    Inventors: Anthony D. AMICANGIOLI, B. Joshua ROSEN, Ryan P. WALSH, Nicola AGUILAR-THOMAS
  • Publication number: 20240007404
    Abstract: A distributed computing system, such as may be used to implement an electronic trading system, controls inbound message flow rates. Limiting a per-client or per-connection inbound message rate also helps ensure fair provisioning of computing resources, so that a single client's excessive use of resources cannot overwhelm the system to such an extent that it prevents other clients from interacting with the distributed system. It is also desirable to have system-wide control of the overall inbound message rate across all client connections. Such system-wide control ensures that the distributed system as a whole can maintain the required levels of service, including offering a predictable level of access for all clients.
    Type: Application
    Filed: August 5, 2021
    Publication date: January 4, 2024
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen
  • Publication number: 20230396559
    Abstract: A distributed computing system, such as may be used to implement an electronic trading system, supports a notion of fairness in latency. The system does not favor any particular client. Thus, being connected to a particular access point into the system (such as via a gateway) does not give any particular device an unfair advantage or disadvantage over another. That end is accomplished by precisely controlling latency, that is, the time between when request messages arrive at the system and a time at which corresponding response messages are permitted to leave. The precisely controlled, deterministic latency can be fixed over time, or it can vary according to some predetermined pattern, or vary randomly within a pre-determined range of values.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 7, 2023
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen, Christophe Juhasz
  • Publication number: 20230316399
    Abstract: An electronic trading system and corresponding method are based on a point-to-point mesh architecture. The electronic trading system comprises a gateway, core compute node, and sequencer. The core compute node performs an electronic trading matching function. The gateway transmits a message to the core compute node via a first direct connection. The gateway transmits the message via a second direct connection to the sequencer which, in turn, transmits a sequence-marked message to the core compute node via a third direct connection. The core compute node determines relative ordering of the message among other messages in the electronic trading system based on the sequence-marked message to complete the electronic trading matching function, deterministically.
    Type: Application
    Filed: August 5, 2021
    Publication date: October 5, 2023
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen, Christophe Juhasz
  • Publication number: 20230308213
    Abstract: Systems and methods are disclosed herein that provide low latency data communication with improved physical link layer reliability through repeated physical layer retransmission of data over a data connection whenever the connection is idle (i.e., no new data to send). In some embodiments, the transmission of administrative control symbols (e.g. “idles,” “commas”, etc.) can be suppressed or otherwise reduced to allow some of the available connection bandwidth to be used for data redundancy and fault tolerance through the repeated retransmission of data as described in more detail below. Accordingly, instead of executing time-consuming error correcting routines, a receive node can discard the erroneous data frame and process at least one repeat frame that carries the same data payload. Sequence numbers and/or other repeat indicators can be used to distinguish original frames from repeat frames and/or for identifying which frames carry the same data payload.
    Type: Application
    Filed: August 5, 2021
    Publication date: September 28, 2023
    Inventors: Anthony D. AMICANGIOLI, B. Joshua ROSEN
  • Publication number: 20230299864
    Abstract: Systems and methods for clock synchronization are disclosed in which a primary node generates special physical laver clock sync symbols from the output of a reference clock and inserts the clock sync symbols within a symbol stream to one or more secondary nodes. Upon receiving a symbol stream, a secondary node can extract the clock sync symbols from the stream to synchronize its local clock with the reference clock of the primary node. In particular, the clock sync symbols can be inserted into the symbol stream at any arbitrary symbol location, e.g., even between consecutive symbols of a symbol encoded data frame. The clock sync symbols can also replace some control symbols in the symbol stream, such as idle or comma symbols. Accordingly, the clock sync symbols can be inserted into a symbol stream at fixed intervals, irregular intervals, or at any arbitrary time for high resolution clock synchronization.
    Type: Application
    Filed: August 5, 2021
    Publication date: September 21, 2023
    Inventors: Anthony D. AMICANGIOLI, Allen BAST, B. Joshua ROSEN
  • Patent number: 11729107
    Abstract: A distributed computing system, such as may be used to implement an electronic trading system, supports a notion of fairness in latency. The system does not favor any particular client. Thus, being connected to a particular access point into the system (such as via a gateway) does not give any particular device an unfair advantage or disadvantage over another. That end is accomplished by precisely controlling latency, that is, the time between when request messages arrive at the system and a time at which corresponding response messages are permitted to leave. The precisely controlled, deterministic latency can be fixed over time, or it can vary according to some predetermined pattern, or vary randomly within a pre-determined range of values.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: August 15, 2023
    Assignee: HYANNIS PORT RESEARCH, INC.
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen, Christophe Juhasz
  • Patent number: 11483087
    Abstract: Systems and methods for clock synchronization are disclosed in which a primary node generates special physical layer clock sync symbols from the output of a reference clock and inserts the clock sync symbols within a symbol stream to one or more secondary nodes. Upon receiving a symbol stream, a secondary node can extract the clock sync symbols from the stream to synchronize its local clock with the reference clock of the primary node. In particular, the clock sync symbols can be inserted into the symbol stream at any arbitrary symbol location, e.g., even between consecutive symbols of a symbol encoded data frame. The clock sync symbols can also replace some control symbols in the symbol stream, such as idle or comma symbols. Accordingly, the clock sync symbols can be inserted into a symbol stream at fixed intervals, irregular intervals, or at any arbitrary time for high resolution clock synchronization.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 25, 2022
    Assignee: Hyannis Port Research, Inc.
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen
  • Patent number: 11315183
    Abstract: An electronic trading system and corresponding method are based on a point-to-point mesh architecture. The electronic trading system comprises a gateway, core compute node, and sequencer. The core compute node performs an electronic trading matching function. The gateway transmits a message to the core compute node via a first direct connection. The gateway transmits the message via a second direct connection to the sequencer which, in turn, transmits a sequence-marked message to the core compute node via a third direct connection. The core compute node determines relative ordering of the message among other messages in the electronic trading system based on the sequence-marked message to complete the electronic trading matching function, deterministically.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: April 26, 2022
    Assignee: Hyannis Port Research, Inc.
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen, Christophe Juhasz
  • Patent number: 11303389
    Abstract: Systems and methods are disclosed herein that provide low latency data communication with improved physical link layer reliability through repeated physical layer retransmission of data over a data connection whenever the connection is idle (i.e., no new data to send). In some embodiments, the transmission of administrative control symbols (e.g., “idles,” “commas”, etc.) can be suppressed or otherwise reduced to allow some of the available connection bandwidth to be used for data redundancy and fault tolerance through the repeated retransmission of data as described in more detail below. Accordingly, instead of executing time-consuming, error correcting routines, a receive node can discard the erroneous data frame and process at least one repeat frame that carries the same data payload. Sequence numbers and/or other repeat indicators can be used to distinguish original frames from repeat frames and/or for identifying which frames carry the same data payload.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: April 12, 2022
    Assignee: Hyannis Port Research, Inc.
    Inventors: Anthony D. Amicangioli, B. Joshua Rosen
  • Publication number: 20220044319
    Abstract: An electronic trading system and corresponding method are based on a point-to-point mesh architecture. The electronic trading system comprises a gateway, core compute node, and sequencer. The core compute node performs an electronic trading matching function. The gateway transmits a message to the core compute node via a first direct connection. The gateway transmits the message via a second direct connection to the sequencer which, in turn, transmits a sequence-marked message to the core compute node via a third direct connection. The core compute node determines relative ordering of the message among other messages in the electronic trading system based on the sequence-marked message to complete the electronic trading matching function, deterministically.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen, Christophe Juhasz
  • Publication number: 20220045964
    Abstract: A distributed computing system, such as may be used to implement an electronic trading system, supports a notion of fairness in latency. The system does not favor any particular client. Thus, being connected to a particular access point into the system (such as via a gateway) does not give any particular device an unfair advantage or disadvantage over another. That end is accomplished by precisely controlling latency, that is, the time between when request messages arrive at the system and a time at which corresponding response messages are permitted to leave. The precisely controlled, deterministic latency can be fixed over time, or it can vary according to some predetermined pattern, or vary randomly within a pre-determined range of values.
    Type: Application
    Filed: June 18, 2021
    Publication date: February 10, 2022
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen, Christophe Juhasz
  • Publication number: 20220045955
    Abstract: A distributed computing system, such as may be used to implement an electronic trading system, controls inbound message flow rates. Limiting a per-client or per-connection inbound message rate also helps ensure fair provisioning of computing resources, so that a single client's excessive use of resources cannot overwhelm the system to such an extent that it prevents other clients from interacting with the distributed system. It is also desirable to have system-wide control of the overall inbound message rate across all client connections. Such system-wide control ensures that the distributed system as a whole can maintain the required levels of service, including offering a predictable level of access for all clients.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen
  • Publication number: 20220045790
    Abstract: Systems and methods are disclosed herein that provide low latency data communication with improved physical link layer reliability through repeated physical layer retransmission of data over a data connection whenever the connection is idle (i.e., no new data to send). In some embodiments, the transmission of administrative control symbols (e.g., “idles,” “commas”, etc.) can be suppressed or otherwise reduced to allow some of the available connection bandwidth to be used for data redundancy and fault tolerance through the repeated retransmission of data as described in more detail below. Accordingly, instead of executing time-consuming, error correcting routines, a receive node can discard the erroneous data frame and process at least one repeat frame that carries the same data payload. Sequence numbers and/or other repeat indicators can be used to distinguish original frames from repeat frames and/or for identifying which frames carry the same data payload.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Inventors: Anthony D. Amicangioli, B. Joshua Rosen
  • Publication number: 20220045777
    Abstract: Systems and methods for clock synchronization are disclosed in which a primary node generates special physical layer clock sync symbols from the output of a reference clock and inserts the clock sync symbols within a symbol stream to one or more secondary nodes. Upon receiving a symbol stream, a secondary node can extract the clock sync symbols from the stream to synchronize its local clock with the reference clock of the primary node. In particular, the clock sync symbols can be inserted into the symbol stream at any arbitrary symbol location, e.g., even between consecutive symbols of a symbol encoded data frame. The clock sync symbols can also replace some control symbols in the symbol stream, such as idle or comma symbols. Accordingly, the clock sync symbols can be inserted into a symbol stream at fixed intervals, irregular intervals, or at any arbitrary time for high resolution clock synchronization.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Inventors: Anthony D. Amicangioli, Allen Bast, B. Joshua Rosen