Patents by Inventor Børge Svingen

Børge Svingen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7330857
    Abstract: In a search engine with two-dimensional scalable architecture for searching of a collection of documents, the search engine comprises data processing units which forms set of nodes connected in a network, a first set of nodes comprising dispatch nodes, a second set of nodes search nodes and a third set of nodes indexing nodes. The search nodes are grouped in columns, which via the network are connected in parallel between the dispatch nodes and an indexing node. The dispatch nodes are adapted for processing search queries and search answers, the search nodes are adapted to contain search software, at least some of the search nodes additionally including at least one search processor module and the indexing nodes are adapted for generally generating indexes for the search software. Optionally, acquisition nodes provided in a fourth set of nodes and adapted for processing the search answers, thus relieving the dispatch nodes of this task.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: February 12, 2008
    Assignee: Overture Services, Inc.
    Inventors: Børge Svingen, Knut Magne Risvik, Arne Halaas, Tor Egge
  • Patent number: 6760744
    Abstract: A digital processing system P, configured as a regular tree with n+1 levels S0, S1, S2 . . . Sn and degree k, provided in the form of a circuit Pn on the level Sn and forms the root node of the tree, an underlying level Sn−q, q=1,2, . . . n−1, in the circuit P provided nested in the Kq−1 circuits Pn−q+1 on the overlying level Sn−q+1, each circuit Pn−q+1 on this level including k circuits Pn−q. A q=n defined zeroth level in the circuit Pn includes from Kn−1+1 to Kn circuits P0 which form kernel processors in the processing device P and on the level S0 and constitute the leaf nodes of the tree, the kernel processor P0 being provided nested in each of the circuits p1 on the level S1. Each of the circuits P1, P2, . . . Pn, includes a logic unit E which generally is connected with circuits P0, P1, . . . Pn−1. Each of the circuits P0, P1, . . . Pn has additionally identical interfaces I, such that IP0−IP1− . . .
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: July 6, 2004
    Assignee: Fast Search & Transfer ASA
    Inventors: Arne Halaas, Børge Svingen, Geirr I. Leistad
  • Patent number: 6587852
    Abstract: A non-numeric coprocessor for fuzzy information retrieval and pattern recognition has means for information processing and is connectable to a host computer and a data source. A plurality of internal processing elements are organized in a number of simultaneously operable window modules (W0, W1, . . . ) a arranged for inspecting data streams from said source. The processing elements compare data stream bytes with predetermined upper and lower bounds, to decide whether a byte is within said bounds, and, if so, to produce a hit signal. Each window module has a window match logic for correlating hit signals from its different processing elements, and to produce a window match signal, by the occurrence of a predefined match.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: July 1, 2003
    Assignee: Fast Search & Transfer ASA
    Inventors: Børge Svingen, Arne Halaas, Olaf Birkeland