Abstract: A chip is described that incorporates a distributed bus architecture which enable packets of data to be communicated between multiple source/destination nodes. The chip can be designed such that each source/destination node monitors a connecting path (e.g., bus) for receipt of a packet of data. And, upon receiving a packet of data at one of the source/destination nodes, that source/destination node then determines whether the packet of data is addressed to that node. If the packet of data is addressed to that source/destination node, then that node takes the data from the packet of data. Otherwise, if the packet of data is not addressed to that source/destination node, then that node transmits the packet of data on the connecting path to a neighboring source/destination node. The source/destination nodes can also insert data into a packet of data addressed to another source/destination node. Also described are methods for making and using the chip.