Patents by Inventor Baal Yang

Baal Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250275054
    Abstract: A device includes a printed circuit board (PCB) including a signal trace electrically coupled to a signal via. The device further includes a coaxial ground shield configured to reduce signal interference with respect to the signal via. The coaxial ground shield includes a ground via formed in the PCB substantially surrounding the signal via and substantially coaxial with the signal via. The coaxial ground shield further includes metal plating on a wall of the ground via. The metal plating is electrically coupled to a ground plane of the PCB. The coaxial ground shield further includes resin at least partially filling the ground via.
    Type: Application
    Filed: February 27, 2024
    Publication date: August 28, 2025
    Inventors: Tibet Zhao, Baal Yang, Yongwei Chen, Jiawei Zeng
  • Patent number: 12345778
    Abstract: A system for testing multiple devices includes a connector holder having a plurality of holes, wherein each hole included in the plurality of holes is configured to hold a respective cable connector that connects to a cable; a device holder that is configured to hold a first device in a testing position; and an engagement mechanism that supports the connector holder and is operable to move the connector holder to an engaged position, wherein when the first device is being held by the device holder in the testing position, and a first hole included in the plurality of holes holds a first cable connector, a contact point associated with the first cable connector contacts a signal pad associated with the first device.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: July 1, 2025
    Assignee: NVIDIA CORPORATION
    Inventors: Yongwei Chen, Baal Yang, Tibet Zhao
  • Publication number: 20250212317
    Abstract: A device includes a printed circuit board (PCB) including a signal trace electrically coupled to a signal via. The device further includes a slot ground configured to reduce signal interference with respect to the signal via. The slot ground includes a slot formed in the PCB at least partially surrounding the signal via. The slot ground further includes metal plating on a wall of the slot. The metal plating is electrically coupled to a ground plane of the PCB. The slot ground further includes resin at least partially filling the slot.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Inventors: Tibet Zhao, Baal Yang, Yongwei Chen
  • Publication number: 20240241191
    Abstract: A system for testing multiple devices includes a connector holder having a plurality of holes, wherein each hole included in the plurality of holes is configured to hold a respective cable connector that connects to a cable; a device holder that is configured to hold a first device in a testing position; and an engagement mechanism that supports the connector holder and is operable to move the connector holder to an engaged position, wherein when the first device is being held by the device holder in the testing position, and a first hole included in the plurality of holes holds a first cable connector, a contact point associated with the first cable connector contacts a signal pad associated with the first device.
    Type: Application
    Filed: July 22, 2022
    Publication date: July 18, 2024
    Inventors: Yongwei CHEN, Baal YANG, Tibet ZHAO
  • Patent number: 11439010
    Abstract: This disclosure provides a multi-layered printed circuit board (PC) that has signal array region. The signal array region has a width and circumscribes a power core region and has signal vias connected to respective signal ball pads, and ground vias connected to respective ground ball pads within the signal array region that have an associated ball pad pitch. The PCB also has an inner current power layer. The signal and ground vias are arranged on the component layer in a pattern and extend into the inner current layer. The pattern forms current power paths across the width of the signal array region, such that the current power paths have a width that is at least about 50% as wide as the ball pad pitch.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 6, 2022
    Assignee: Nvidia Corporation
    Inventors: Baal Yang, Daniel Lin, Sunil Sudhakaran
  • Publication number: 20210243895
    Abstract: This disclosure provides a multi-layered printed circuit board (PC) that has signal array region. The signal array region has a width and circumscribes a power core region and has signal vias connected to respective signal ball pads, and ground vias connected to respective ground ball pads within the signal array region that have an associated ball pad pitch. The PCB also has an inner current power layer. The signal and ground vias are arranged on the component layer in a pattern and extend into the inner current layer. The pattern forms current power paths across the width of the signal array region, such that the current power paths have a width that is at least about 50% as wide as the ball pad pitch.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 5, 2021
    Inventors: Baal Yang, Daniel Lin, Sunil Sudhakaran