Abstract: Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a stack of layers coupled by at least fusion bonds; a package substrate coupled to a first layer in the stack of layers; one or more dies in the first layer; and one or more dies in a second layer in the stack of layers, the second layer coupled to the first layer, wherein: a copper lining is between adjacent surfaces of any two adjacent dies in at least one of the first layer and the second layer, and the copper lining contacts and substantially covers the adjacent surfaces. In various embodiments, the dies comprise dummy dies and integrated circuit (IC) dies, the dummy dies are one of: semiconductor dies without any ICs, and semiconductor dies having non-functional ICs, and the IC dies comprise semiconductor dies having functional ICs.

Abstract: Embodiments herein relate to a semiconductor package or a semiconductor package structure that includes an interposer with opposing first and second sides. A memory and a processing unit may be coupled with the second side of the interposer, and the first side of the interposer may be to couple with the substrate. The processing unit and memory may be communicatively coupled with one another and the substrate by the interposer. Other embodiments may be described or claimed.

Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.

Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.

Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.

Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.