Abstract: Detecting a defect on a storage device is disclosed. Detecting includes receiving a signal read from a storage device, sampling the signal to obtain a set of signal samples, wherein the sampling starts at an arbitrary time, computing a defect value for a defect type using the set of signal samples, comparing the defect value with a threshold associated with the defect type, determining whether there is a defect of the defect type based at least in part on the comparison, and in the event that a defect is detected, outputting an indication associated with the defect.

Abstract: Detecting a defect on a storage device is disclosed. Detecting includes receiving a signal read from a storage device, sampling the signal to obtain a set of signal samples, wherein the sampling starts at an arbitrary time, computing a defect value for a defect type using the set of signal samples, comparing the defect value with a threshold associated with the defect type, determining whether there is a defect of the defect type based at least in part on the comparison, and in the event that a defect is detected, outputting an indication associated with the defect.

Abstract: Detecting a defect on a storage device is disclosed. Detecting includes receiving a signal read from a storage device, sampling the signal to obtain a set of signal samples, wherein the sampling starts at an arbitrary time, computing a defect value for a defect type using the set of signal samples, comparing the defect value with a threshold associated with the defect type, determining whether there is a defect of the defect type based at least in part on the comparison, and in the event that a defect is detected, outputting an indication associated with the defect.

Abstract: Circuitry for detecting and recording latches in read bias current may include circuitry for generating a reference voltage, a pair of current to voltage converters to convert the bias and reference currents to voltage signals, a comparator to compare those two voltages, a latch to latch the compared signal, and a counter/register to count and store the number of glitches that have been detected. It may be possible to read from the register the number of detected glitches to be used in diagnosing faults in the disk drive system. In addition, it may be possible to provide a reset input to the register to zero the counter.

Abstract: The present invention is a method and apparatus for removing transient DC level shifts caused by thermal asperities. A read signal is generated by a transducer in response to proximate contact between the transducer and magnetic flux fields recorded on a magnetic media surface. The read signal is provided to a continuous time filter and a sampler. During normal operation, the output of the sampler is provided directly to a fixed delay tree search detector. Upon encountering a thermal asperity, the output of the sampler is first provided to a 1-D sampled filter which removes the DC shift caused by the thermal asperity and then to the fixed delay tree search detector, which provides signal recovery. A multiplexer provides selection of the output signal from between sampler and the 1-D sample filter.

Abstract: A method and apparatus is disclosed for removing transient DC level shifts caused by thermal asperities (TAs), thereby reducing TA induced errors. Read signal generated by a Magneto resistive (MR) is input to a continuous time filter and a sampler. Sampler output is input to a 1-D sampled filter which performs level equalization to remove DC Shift cased by TA disturbance. Sampled filter output is input to MUX along with sampler outputs. MUX selects sampled filter output during TAs. MUX output is input to a FIR filter and Viterbi decoder. Gain and Timing loop tracking and acquisition blocks receive sampler and FIR filter output and output correction signals for use by VGA and phase/frequency Detector.

Abstract: An analog receiver circuit suitable for use with a flash analog-to-digital converter is described. A first stage of the receiver acts essentially as a voltage follower, receiving the centertap voltage of a flash A/D converter resistor ladder, and maintaining an internal reference voltage substantially equal to the centertap voltage over time. A second stage of the analog receiver acts as centering means, receiving an analog signal and centering it with respect to the internal reference voltage provided by the first stage. The receiver is thus able to provide an analog signal to the flash A/D converter which is dynamically centered with respect to the converter's operating voltage, thereby reducing DC offset. Moreover, introducing the analog signal at the second stage minimizes the bandwidth-limiting elements between this input signal and the DC-centered output signal. Thus DC offset is further reduced and operating frequencies of 500 MTz or greater are possible.