Abstract: A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.

Abstract: A bias generator unit is provided that includes a central bias generator to provide a bias voltage, a local bias generator to receive the bias voltage and a reference voltage and to provide a forward body bias signal or a reverse body bias signal. The bias generator may include a charge pump to output (or provide) a reference voltage to a reference generator, which in turn provides reference signals to the central bias generator. As a result, the local bias generator may control the body bias signal provided by the local bias generator.

Abstract: A method and apparatus are provided for adjusting a frequency of a die. This may include measuring characteristics of a die at various combinations of power supply voltage, body bias voltage and/or temperature and determining operating characteristics, such as power supply voltage and body bias voltage, based on the measured characteristics.

Abstract: A bias generator unit is provided that includes a central bias generator to provide a bias voltage, a local bias generator to receive the bias voltage and a reference voltage and to provide a forward body bias signal or a reverse body bias signal. The bias generator may include a charge pump to output (or provide) a reference voltage to a reference generator, which in turn provides reference signals to the central bias generator. As a result, the local bias generator may control the body bias signal provided by the local bias generator.

Abstract: A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.

Abstract: In some embodiments, a method includes providing an integrated circuit (IC) die in a package. The IC die may have a metal layer on a back surface of the IC die. The method may also include applying a bias signal to the IC die via the metal layer.

Abstract: In some embodiments, a method includes providing an integrated circuit (IC) die in a package. The IC die may have a metal layer on a back surface of the IC die. The method may also include applying a bias signal to the IC die via the metal layer.

Abstract: A local bias generator generates forward body bias that tracks variations in a supply voltage of a functional block containing one or more circuits having field-effect transistors. The bias is generated using a single-stage source-follower formed from a pair of matched transistors. In operation, the transistors convert a first bias signal into a second bias signal based on a difference between the supply voltage and a reference voltage. The first bias signal and reference voltage may be generated by a central bias generator.

Abstract: An instruction translation look-aside buffer (iTLB) for attaining very high data processing throughput comprises a 2.sup.n -way set associative data array having m sets, where m and n are both integers greater than or equal to one, with associated data and tag arrays. A set address selects one of the m sets for reading, resulting in a readout of all 2.sup.n ways of the tag, valid and data arrays. Comparison logic determines if a match exists between the 2.sup.n tags read out from the tag array with a portion of the linear address. A "hit" to a certain way causes a hit line signal to select data for the corresponding way, which is output from a 2.sup.n :1 static multiplexer and contains the physical address translation. Each of the hit lines are precharged during a first phase of a clock cycle. The comparison logic operating during a second phase of a clock cycle. Thus, the matching is accomplished in a single clock cycle.