Abstract: The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that receives an enable signal and generates a latch input. A latch is coupled to the first logic gate and receives the latch input and a clock input. The latch includes a tri-state inverter and an inverting logic gate. The tri-state inverter is activated by a control signal generated by the inverting logic gate. A second logic gate receives the control signal and generates a gated clock.

Abstract: A multi-bit interlace latch includes a first and second latch that each have redundant active feedback paths to reduce the incidence of soft-errors. The first and second latches have active circuitry that includes nodes that are susceptible to radiation-induced soft errors. Active circuitry from the second latch is interlaced between active circuitry of the first latch to increase the isolation between critical nodes of the first latch. While the second latch circuit increases isolation between critical nodes of the first latch, the first latch may also benefit the second latch by increasing the isolation between critical nodes of the first latch as well.

Abstract: An exemplary functional input sequential circuit for reducing the setup time of input signals. The functional sequential circuit includes a tri-state inverter having an input signal and two control signals. The transmission circuit receives a control signal from a combinational logic circuit that performs a logical operation on a second input signal and a clock signal. The output of the transmission circuit is coupled to a digital storage element. Further, a control circuit is coupled to the digital storage element in order to force a value on the digital storage element when no input signal is received from the transmission circuit. The control circuit is also controlled by the second input signal and a clock signal.