Patents by Inventor Badong Chen

Badong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10911522
    Abstract: A parallel computing system is provided, including input ports, a first switching network, a computing array, a second switching network and output ports. The first switching network is receiving input data from the input ports, sequencing the input data according to different computing modes of the computing array and outputting sequenced input data; the computing array is performing parallel computation on the sequenced input data and outputting intermediate data; and the second switching network is sequencing the intermediate data according to different output modes and outputting sequenced intermediate data through the output ports. The present disclosure applies the switching networks to the parallel computing system and performs any required sequencing on the input or output data according to the different computing modes and output modes to complete various arithmetic operations through the computing array after the input data are input into the computing array.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: February 2, 2021
    Assignee: Xi'an Jiaotong University
    Inventors: Pengju Ren, Long Fan, Boran Zhao, Pengchen Zong, Wenzhe Zhao, Fei Chen, Badong Chen, Nanning Zheng
  • Publication number: 20200120154
    Abstract: A parallel computing system is provided, including input ports, a first switching network, a computing array, a second switching network and output ports. The first switching network is receiving input data from the input ports, sequencing the input data according to different computing modes of the computing array and outputting sequenced input data; the computing array is performing parallel computation on the sequenced input data and outputting intermediate data; and the second switching network is sequencing the intermediate data according to different output modes and outputting sequenced intermediate data through the output ports. The present disclosure applies the switching networks to the parallel computing system and performs any required sequencing on the input or output data according to the different computing modes and output modes to complete various arithmetic operations through the computing array after the input data are input into the computing array.
    Type: Application
    Filed: November 14, 2018
    Publication date: April 16, 2020
    Inventors: Pengju REN, Long Fan, Boran Zhao, Pengchen Zong, Wenzhe Zhao, Fei Chen, Badong Chen, Nanning Zheng
  • Patent number: 9924153
    Abstract: A parallel synchronous scaling engine for multi-view 3D display and a method thereof are provided, wherein selection and combination calculation are provided to an interpolation pixel window, then interpolation calculation is provided to a combined interpolation pixel window of a combined view field, calculation results are directly displayed on a display terminal. That is to say, interpolation is originally provided before stereoscopic pixel rearrangement, which is now improved, in such a manner that screening and combination of pixel points is provided before interpolation calculation. According to the present invention, computation and memory resource is greatly saved. The method is suitable to be implemented by hardware, for satisfying various numbers of viewpoints and interpolation algorithm, and being compatible with multi-view 3D display with the integrated and floating-point pixel arrangement, wherein the computation resource does not need to be increased with increasing of the viewpoints.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: March 20, 2018
    Assignee: XI'AN JIAOTONG UNIVERSITY
    Inventors: Pengju Ren, Xiaogang Wu, Hongwei Bi, Hang Wang, Hongbin Sun, Badong Chen, Nanning Zheng